Types of GPIO
The Topaz
FPGA supports
the
following types of GPIO:
- High-voltage I/O (HVIO)—Simple I/O blocks that can support single-ended I/O standards.
- High-speed I/O (HSIO)—Complex I/O blocks that can support single-ended and differential I/O functionality.
- Enhanced high-speed I/O (HSIO2)—Complex I/O blocks that can support single-ended and differenttial I/O functionality as well as XXX.
The I/O logic comprises three register types:
- Input—Capture interface signals from the I/O before being transferred to the core logic
- Output—Register signals from the core logic before being transferred to the I/O buffers
- Output enable—Enable and disable the I/O buffers when I/O used as output
The HVIO supports the following I/O standards.
| Standard | VCCIO33 (V) | When Configured As |
|---|---|---|
| LVTTL 3.3 V | 3.3 | GPIO |
| LVTTL 3.0 V | 3.0 | GPIO |
| LVCMOS 3.3 V | 3.3 | GPIO |
| LVCMOS 3.0 V | 3.0 | GPIO |
| LVCMOS 2.5 V | 2.5 | GPIO |
| LVCMOS 1.8 V | 1.8 | GPIO |
Important: Efinix recommends that you limit the number of 3.0/3.3
V HVIO and 2.5 V HVIO as bidirectional or output to 6 per bank to avoid switching
noise. The Efinity® software issues a warning if you exceed the
recommended limit.
The HSIO supports the following I/O standards.
| Standard | VCCIO (V) | VCCAUX (V) | VREF (V) | When Configured As | |
|---|---|---|---|---|---|
| TX | RX | ||||
| LVCMOS 1.8 V | 1.8 | 1.8 | 1.8 | – | GPIO |
| LVCMOS 1.5 V | 1.5 | 1.5 | 1.8 | – | GPIO |
| LVCMOS 1.2 V | 1.2 | 1.2 | 1.8 | – | GPIO |
| HSTL/Differential HSTL 1.8 V SSTL/Differential SSTL 1.8
V |
1.8 | 1.8 | 1.8 | 0.5 * VCCIO | GPIO |
| HSTL/Differential HSTL 1.5 V SSTL/Differential SSTL 1.5
V |
1.5 | 1.5, 1.81 | 1.8 | 0.5 * VCCIO | GPIO |
| SSTL/Differential SSTL 1.35 V | 1.35 | 1.35, 1.5, 1.81 | 1.8 | 0.5 * VCCIO | GPIO |
| HSTL/Differential HSTL 1.2 V SSTL/Differential SSTL 1.2
V |
1.2 | 1.2, 1.35, 1.5, 1.81 | 1.8 | 0.5 * VCCIO | GPIO |
| LVDS/RSDS/mini-LVDS | 1.8 | 1.5, 1.81 | 1.8 | – | LVDS |
| Sub-LVDS | 1.8 | 1.5, 1.81 | 1.8 | – | Sub-LVDS |
| MIPI | 1.2 | 1.2 | 1.8 | – | MIPI Lane |
| SLVS | 1.2 | 1.2 | 1.8 | – | SLVS |
The differential receivers are powered by VCCAUX, which gives you the flexibility to choose the VCCIO you want to use. However, you must comply to the requirements stated in the previous table.
1 To prevent pin leakage, you must ensure
that the voltage at the pin does not exceed VCCIO.