Transceiver PLLs
- Two common PLLs that are shared by all lanes in the quad
- Four lane-based PLLs, one for each lane
These PLLs are driven by one or more reference clocks, refclk0 and
refclk1. refclk0 can feed both common PLLs, while
refclk1 only feeds common PLL 1. You specify the reference clocks
in the Quad-Lane Settings dialog box (see Quad-Lane Settings).
The following figures show the block diagrams for the common and lane PLLs.
Because the transceiver protocols have different PLL requirements, and they share the common PLLs, there are some restrictions on which protocols you can use together in the same quad. All of the lanes in the same transceiver quad must have the same common PLL settings. For example:
- A PMA Direct lane with a 100-Mhz reference clock, 1.25-Gbps data rate, and 20-bit SerDes width can share the same common PLL as the Ethernet protocols because they all use the same common PLL settings (M = 50 and O = 6).
- A PMA Direct lane with a 100-Mhz reference clock, 2.7-Gbps data rate, and 20-bit SerDes width cannot share the same common PLL as the Ethernet protocols because the common PLL settings are different (M = 48 and O = 4 for PMA Direct and M = 50 and O = 6 for Ethernet).
Because the transceiver quad has two common PLLs, you can have protocols with mismatched common PLL settings in the same quad as long as you do not need more than two common PLLs total. For example, a PMA Direct lane with a 100-Mhz reference clock, 2.7-Gbps data rate, and 20-bit SerDes width can share the same transceiver quad as the Ethernet protocols as long as both common PLLs are available (one for PMA Direct and one for Ethernet).