Using the PLL Block

The Topaz FPGA's PLL block lets you configure the reference clock, feedback options, frequency, and output clocks for the PLL. This PLL is referenced as PLL_V3 in the Python API. You set up the PLL using the PLL Clock Calculator, which provides an easy-to-use graphical way to specify the frequencies and other settings.

  • In the PLL's Properties tab, you specify general settings such as the instance name, PLL resource, clock source, and external clock.
  • You can invert any of the clock outputs by clicking Inverted for the clock output in the Output Clock Inversion box.
  • Click the Automated Clock Calculation button to open the PLL Clock Calculator.

Reference Clock Settings

The PLL has four possible reference clocks. Depending on the PLL, one or two of the clocks can come from the FPGA core, and two or three can come from off chip. You select the clocks using the Clock Source drop-down box:

  • core—The PLL reference clock comes from the FPGA core.
  • external—Enables clock 0, 1, or 2. The PLL reference clock comes from an external pin. The GUI displays the resource(s) that can be the reference clock.
    Note: In this mode, a GPIO block with a pll_clkin connection type must generate the reference clock(s). The software displays which resource(s) you can use (and the instance name if you have created it).
    1. Add a GPIO block.
    2. Enter the instance name.
    3. Choose input as the mode.
    4. Choose pll_clkin as the connection type.
    5. In the Resource Assigner, assign it to the resource shown in the PLL's Properties tab.
  • dynamic—Enables all four clocks; requires a clock selector bus to choose the clock dynamically. The GUI displays the resource(s) that can be the reference clock.