Design Check: PMA Direct Messages

When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error messages you may encounter and explains how to fix them.

pma_direct_custom_data_rate (error)

Message Invalid data rate: Value, <value> out of range (min=<min>, max=<max>)
Invalid calculated data rate: Value, <value> out of range (min=<min>, max=<max>)
To fix Change the value for the data rate in the Quad Lane Settings dialog box.

pma_direct_custom_data_rate (warning)

Message Mismatch clock serializer frequency with data rate. Requested: <data rate value> Gbps, Calculated: <serializer frequency> Gbps
Mismatch parallel clock frequency. Requested <frequency>, Calculated: <frequency>
To fix Change the value for the data rate or frequency in the Quad Lane Settings dialog box.

pma_direct_rule_bonding_mode (error)

Message Bonding mode <x2,x4> requires <2,4> lanes configured in the same QUAD
To fix Bonding mode x2 requires 2 lanes in the same quad to be configured; bonding mode x4 requires 4 lanes in the same quad to be configured
Message Bonding mode x2 is valid on lane resource pairs LN0,LN1 or LN2,LN3 of the same QUAD only
To fix Only certin lanes can be bonded together. Check that the lanes you are trying to bond are set to the correct resources. Refer to "Bonding Mode" in the Titanium PMA Direct User Guide for details.
Message Mismatch properties against lane instances in the same bonding <bonding_mode>: <list of mismatched parameters>
To fix Lanes that are bonded must have the same preperties. Update the listed parameters to ensure that the highlighted mismatched properties are identical for all PMA Direct lane instances within the same bond
Message Bonding mode x8 requires all lanes in the quad to be configured
To fix Create new instances and assign remaining resource in the same quad, or change the lane bonding mode. Bonding mode x8 requires you to configure all 4 lanes in 2 quads.
Message Expected Q# lanes to be configured as part of bonding mode x8
To fix Create new instances and assign resources for the quad, or change the bonding mode. Bonding mode x8 can only use quad pairs from the following list: (Q0, Q1), (Q2, Q3), (Q1, Q2).
Message Bonding mode x8 requires 8 lane instances to be configured
Bonding mode x8 requires 8 lane instances but found <number of instances>
To fix Change the bonding mode for the other lane instance to ensure that there are 8 PMA Direct instances with bonding mode x8 for the correct quad-lane resource assignments For x8 mode, (Q0, Q1), (Q2, Q3), (Q1, Q2) are the available quad pairs.
Message Clock resource is not selected for bonding mode <bonding mode>
To fix Turn on the Used as Clock Resource option for one of the PMA Direct instances in the Pins tab > Clock and Reset subtab.
Message Only 1 clock resource is allowed to be selected for bonding mode <bonding mode>, selected instances: <list of instances>
To fix You can only use one PMA Direct clock as a clock signal to the core.Turn off the Used as Clock Resource for all the listed instances except for the one that you want to use as a clock resource.

pma_direct_rule_data_rate_timing_model (error)

Message Data rate greater than <max limit> Gbps is not supported in timing model <speed grade>
To fix Choose a lower data rate or select a device/timing model that supports the data rate. Refer to the "Transceiver Specifications" topic in the data sheet for supported rates by speed grade.

pma_direct_rule_external_clock (error)

Message PLL LC0 is fixed to be driven by reference clock 0
To fix In the <project>.peri.xml file, update the value of PMA_CMN__cmn_plllc_gen_preg__cmn_plllc_pfdclk1_sel_preg to Refclk 0.

pma_direct_rule_hw_drc (error)

Message Invalid value assigned to the following parameters: <list_of_parameters>
Found <#> HW Errors: <list_of_errors>
To fix Enter valid values for the parameters.

pma_direct_rule_hw_drc (warning)

Message Found <#> HW Warnings: <list_of_errors>
To fix Enter valid values for the parameters.

pma_direct_rule_inst_name (error)

Message Instance name is empty.
Valid characters are alphanumeric characters with dash and underscore only
To fix Enter a valid pin name.

pma_direct_rule_invalid_hex_value (error)

Message The following hexadecimal parameters has invalid value: <list_of_parameters_with_error_message>
To fix Update the parameters to use a hexadecimal value in a valid range.

pma_direct_rule_osc_clock (error)

Message Oscillator is required to be configured
To fix Create an Oscillator instance with no enable pin.

pma_direct_rule_preset (error)

Message Preset reference clock frequency, <frequency value> does not match with common refclk frequency <frequency value>
To fix Update the preset reference clock frequency or the common reference clock frequeny in the Quad-Lane Settings dialog box.
Message Preset has invalid PLL lane config settings. Please reassign the preset: <list of lane params>
To fix Use a different preset in the Quad-Lane Settings dialog box.
Message Invalid PMA Direct preset with combination of Data Rate: <data rate>, SerDes Width: <serdes width> and Reference Clock Frequency: <reference clock freq> MHz
To fix Change the reference clock frequeny or choose a different preset in the Quad-Lane Settings dialog box.
Message Internal Eror: No PMA Direct PLL configuration map
To fix Contact your local Efinix representative for help.

pma_direct_rule_rclk (error)

Message Use global clock due to unroutable clock loopback on regional clock with bonding mode:<bonding_mode> Mode: <mode> on pins: <list of pin types>
To fix Change the connection type for the listed pin types

pma_direct_rule_resource (error)

Message Resource name is empty
To fix Assign a resource.
Message Resource is not a valid PMA Direct device instance
To fix Assign the instance to a resource that exists in the device.

pma_direct_rule_resource_excluded (error)

Message Resource <resource> is excluded in Package Planner. Please use another resource
To fix The pins for the affected resource have been excluded in the Package Planner, and cannot be assigned. Remove the excluded setting in the Package Planner or choose another resource.

pma_direct_rule_res_usage (error)

Message Resource name conflict with instance <instance name>
To fix The resource is already used. Choose another one.
Message Resource conflicts with PCI Express resource <resource name>
To fix You cannot use the same resource for PCI Express and PMA Direct at the same time. Update one of the resources. (PCI Express uses quad 0 and quad 2.)

pma_direct_rule_rx_clock (error)

Message Interface Receive Clock Input pin name cannot be empty on lane with clock resource enabled
To fix Add a pin name for the instance in the Block Editor > Pins > Interface Receive Clock Input Pin Name box.

pma_direct_rule_rx_register_bonding_mode (error)

Message Rx Register mode only supports bonding mode x1
To fix For PMA Direct blocks, if Control Register tab > Mode is set to TX FIFO, RX Register, you cannot use x2, x4, or x8 bonding modes. Instead, choose x1 for the Bonding Mode option.

pma_direct_rule_rx_tdms_clk (error)

Message Enable TMDS forwarded clock out to core is only supported with Bonding Mode x4
To fix Choose x4 in the PMA Direct block's Control Register > Bonding Mode drop-down-list box. See PMA Direct Bonding Mode.
Message Enable TMDS forwarded clock out to core is only supported with Mode Rx FIFO and Tx FIFO, Rx FIFO
To fix When you enable TDMS, you need to use the TX FIFO, RX FIFO or RX FIFO Only for the Control Register > Mode setting.
Message Enable TMDS forwarded clock out to core cannot be used on lane that has the clock resource enabled in a bond
To fix The lane instance that has TMDS enabled cannot be used with the lane that has the Enable clock resource turned on.
Message Interface Receive Clock Input pin name cannot be empty when used with Enable TMDS forwarded clock out to core
To fix If the lane instance has TMDS enabled, you must also specify the receive clock input pin name.

pma_direct_rule_tx_clock (error)

Message Interface Transmit Clock Input pin name cannot be empty
To fix Add a pin name for the instance in the Block Editor > Pins > Interface Transmit Clock Input Pin Name box.
Message Interface Transmit Clock Input cannot be used with bonding mode x8
To fix In x8 mode you cannot use the TX pins. Choose Mode > RX FIFO, which filters out the TX pins. Clear the Interface Transmit Clock Pin Name field.

pma_direct_rule_x8_mode (error)

Message Bonding mode x8 is only supported in Mode RX FIFO
To fix Change the bonding mode and the mode.

pma_direct_rule_x8_mode_rx_clk_conn_type (error)

Message Bonding mode x8 does not support rclk clock input connection type
To fix Change the RX clock input connection type and bonding mode.

pma_direct_rule_x8_quad_pair (error)

Message Bonding mode x8 on quad Q# expected to pair up with instances of one of the following quads: <list of quad names>
Bonding mode x8 on quad Q# expected to pair up with quad Q#
To fix Change the bonding mode for the listed quads, change the bonding mode of the current instance, or use a different quad resource.
Message Bonding mode x8 requires 2 quads with PMA Direct configuration
To fix Change the bonding mode for the other quad resource, or create an instance of another quad resource that adds up to 8 lanes in the bond.

common_quad_lane_rule_inst_name (error)

Message Instance name is empty.
Valid characters are alphanumeric characters with dash and underscore only
To fix Enter a valid pin name.

common_quad_lane_rule_pin_name (error)

Message The following pin(s) is/are identical across different QUAD: <list of pin and resource names>
To fix Check the pin names to in the Block Editor > Common Properties tab to ensure that you are not using the same name(s) as the lane-specific pin(s).

common_quad_lane_rule_apb_clock (error)

Message APB Clock pin cannot be empty
APB Clock pin cannot be empty when APB is enabled
To fix Enter the clock name in the Block Editor > Common Properties > APB tab or turn off the Enable Advanced Peripheral Bus option.

common_quad_lane_rule_on_board_crystal (error)

Message Reference clock should be from on-board crystal when using <resource name>
To fix Assign one of the lane-based instances to Q0 or Q2.

common_quad_lane_rule_pll_common_setting (error)

Message Mismatch settings on the common PLL parameters across lanes: <list of clocks and lanes>
To fix Transceivers in the same quad need to use the same PLL settings.

common_quad_lane_rule_pll_common_setting (info)

Message Refclk 0 drives both PLL LC0 and PLL LC1
To fix This info message says that even though there is only one reference clock (Refclk 0), the software uses two internal transceiver PLLs (LC0 and LC1) to fulfill the lane PLL setting requirements. This setting happens when there are two different PLL LC parameter values used by the lanes in the quad.

common_quad_lane_rule_refclk (error)

Message Found # lane instances using disabled Refclk 1
To fix Open the <project name>.peri.xml and change the value of REFCLK_SEL to Refclk 0.
Message Refclk 0 frequency invalid for instances: <list of instances> and Refclk 1 frequency invalid for instances: <list of instances>
Refclk 0 frequency invalid for instances: <list of instances>
Refclk 1 frequency invalid for instances: <list of instances>
To fix Update reference clock frequency or use a different reference clock for the instances that are shown as invalid in the Quad-Lane Settings dialog box Console.
Message PLL instance with resource <PLL resource list> is required to be configured when reference clock is not from on-board crystal
To fix Create a PLL instance and assign one of the resource listed in the message, or turn on the Reference clock from on-board crystal option in the Quad-Lane Settings dialog box.
Message Either one of the following PLL instance(s) required to enable output clock when reference clock is not from on-board crystal: <list of PLL instances with expected output clock>
To fix Enable the output clock for one of the PLL instances.
Message Either one of the following PLL instance(s) required to use <list of reference clock source> as exteranl reference clock source when PCIe reference clock is not from on-board crystal: <list of PLL instances>
To fix If the reference clock is not from the on-board crystal, you need to set up an external reference clock. Add a PLL block and assign it to one of the listed PLL resources. Then, add a GPIO block as the PLL's reference clock and assign it to the resource shown in the PLL block.
Message Either one of the following PLL instance(s) required to use local feedback mode when reference clock is not from on-board crystal: <list of PLL instances>
To fix Change feedback mode to local for either one of the listed PLL instances.

common_quad_lane_rule_refclk_usage (error)

Message At least 1 lane-based instance have to use reference clock 0
To fix For the transceivers in the same quad, at least one of the lanes must use reference clock 0. Use the Quad-Lane Settings dialog box to adjust the settings.
Message Refclk 1 configured but not used by instances in the quad
To fix Assign one lane-based instance to reference clock 1, or choose the Reference Clock 0 only option in the Quad Lane Settings dialog box. See Quad-Lane Settings

common_quad_lane_rule_phy_reset_pin (error)

Message PHY Quad Reset pin cannot be empty when PHY Quad Reset Pin is enabled
To fix Enter the reset pin name in the PMA Direct block > Common Properties tab > Clock and Reset sub-tab > PMA Quad Reset Pin Name box or turn off the Enable PHY Quad Reset Pin option.

common_quad_lane_rule_pma_direct_x8_refclk (error)

Message Refclk usage in x8 bonding quads not identical: QUAD_# and Quad_#
Refclk frequencies in x8 bonding quads not identical: QUAD_# and QUAD_#
To fix For x8 mode, all lanes in the quads need to use the same reference clock frequency. Update the reference clock frequency for one of the quads.

common_quad_lane_rule_tmds_refclk (error)

Message Reference clock 1 is compulsory with TMDS enabled
To fix Enable both Refclk 0 and 1 in the quad when TMDS is enabled.
Message Reference clock 1 source is required to be set to Internal Core
To fix Use internal core reference clock 1 when TMDS is enabled in the quad.
Message Reference clock 0 source is required to be set to External
To fix Use external reference clock 0 when TMDS is enabled in the quad.
Message All lane instance in quad with TMDS enabled requires using Refclk 1
To fix Choose Refclk1 on all pma direct lanes in the quad with TMDS enabled (only supported on bonding x4).
Message Quad with PMA Direct TMDS enabled instance cannot be mixed with SGMII or XGMII
To fix Since TMDS is only supported on bonding x4, it means all lanes have to have PMA Direct instances with bonding x4.