Using the MIPI DPHY TX Interface

The following tables describe the settings for the Topaz MIPI DPHY TX blocks in the Interface Designer.

Table 1. Base Tab
Parameter	Choices	Notes
PHY bandwidth in Mbps	Integer up to 2500	Specify the bandwidth. Default: 2500
Instance Name	User defined
MIPI TX Resource	None, MIPI_TX0, MIPI_TX1, MIPI_TX2, MIPI_TX3	Choose the resource.
Reference Clock Frequency	12.0, 19.2, 25.0, 26.0, 27.0, 38.4, 52.0	Choose the frequency for the reference clock.
Reference Clock Source Type	core, gpio, pll	Choose which resource generates the reference clock. For gpio and pll, the Block Editor shows you which resource to connect as the reference clock. For core, you specify the clock name.

Table 2. Control/Status Tab
Option	Choices	Notes
Enable Spread Spectrum Clock (SSC)	On or off	Turn on to enable SSC.
SSC Amplitude for MIPI Internal PLL (PPM)	2500 - 4999	Spread-spectrum clock amount in ppm. Default: 4999
SSC Frequency for MIPI Internal PLL (kHz)	30 - 33	Spread-spectrum clock frequency setting. Default: 30
SSC Initial Amplitude for MIPI Internal PLL (PPM)	2501 - 5000	Spread-spectrum clock initial spread down amount in ppm. The initial amplitude value must be larger than the amplitude value. Default: 5000
<description> Pin Name	User defined	Control and status pin names. Efinix recommends that you use the defaults.
HS Transmit Byte/Word Clock Connection Type	gclk, rclk	Choose whether to connect to a global clock (gclk) or regional clock (rclk). Default: gclk
Invert Excape Mode Transmit Clock Pin	On or off	Turn on to invert the clock.

Table 3. Clock Lane Tab
Option	Choices	Notes
Escape Mode Receive Clock Pin Name	User defined	Specify the clock name.
Escape Mode Receive Clock Connection Type	normal, rclk	normal: Default. The clock signal is an input signal to the core. rclk: The clock signal is feeding the regional clock network.
<description> Pin Name	User defined	Clock lane pin names. Efinix recommends that you use the defaults.

Table 4. Data Lane Tab
Option	Choices	Notes
Enable Turn-around Feature in Data Lane 0	On or off	Lane 0 can operate as a bi-directional data lane when this option is on. Default: on
Number of data lanes	1, 2, 4	Choose the number of lanes. Default: 4
Width of the data bus	8, 16	Specify the width. Default: 8
<description> Pin Name	User defined	Data lane pin names. Efinix recommends that you use the defaults.

Table 5. Lane Mapping Tab
Parameter	Choices	Notes
Phy Lane n	clk, data0, data1, data2, data3, unused	The MIPI TX block supports 4 data lanes and 1 clock lane. For each lane, specify whether to use it as clock or data. The lane mapping must be unique, which the software enforces.
Swap P&N Pin	On or off	Turn on to change which pin is P or N. This setting can be helpful when laying out your board.

Table 6. Timing TabEfinix encourages you to maintain the current settings of the timing parameter.
Parameter	Choices	Notes
T_{CYCLE_SEL}	0 - 7	Internal register value.
T_{PLL_FBK_FRA}	0 - 16777215	Internal register value.
T_{PLL_FBK_INT}	0 - 511	Internal register value.
T_{PLL_PRE_DIV}	0 - 3	Internal register value.
T_{CLANE_HS_CLK_POST_TIME}	0 - 255	Internal register value.
T_{CLANE_HS_CLK_PRE_TIME}	0 - 255	Internal register value.
T_{CLANE_HS_PRE_TIME}	0 - 255	Internal register value.
T_{CLANE_HS_TRAIL_TIME}	0 - 255	Internal register value.
T_{CLANE_HS_ZERO_TIME}	0 - 255	Internal register value.
T_{DLANE_HS_PRE_TIME}	0 - 255	Internal register value.
T_{DLANE_HS_TRAIL_TIME}	0 - 255	Internal register value.
T_{DLANE_HS_ZERO_TIME}	0 - 255	Internal register value.