Interface Designer Output Files

When you generate constraint files, the Interface Designer creates the following output files. You can view them in the Interface section of the Result pane.

  • <project name>.interface.csv—Constrains the FPGA design pins used in the interface between the core and the periphery.
  • <project name>.pt.rpt—Provides information about the interface.
  • <project name>.pinout.csv—Contains the board design pinout in CSV format.
  • <project name>.pinout.rpt—Has the board design pinout in a nicely formatted text file format.
  • <project name>.pt_timing.rpt—Timing report for the Topaz™ interface logic.
  • <project name>.pt.sdc—Template SDC file to constrain the FPGA design pins based on the interface configuration.
  • <project name>_template.v—Template Verilog HDL file defining the FPGA design pins based on the interface configuration.