Create a MIPI TX Interface with GCLK or RCLK

About this task

To build a complete MIPI TX interface you need to have at least one data lane and one clock lane. Unlike MIPI RX, they can be in any MIPI group. The following figure shows the blocks used for a complete MIPI TX interface.

Figure 1. MIPI TX Interface
1. Refer to the Efinity® Software User Guide for a listing of available MIPI-related IP cores.
Important: You need to use specific phase shifts for the SLOWCLK, FASTCLK_C, and FASTCLK_D output clocks from the PLL as shown in step 1 below.

Procedure

  1. Add a PLL block with the following settings:
    OptionDescription
    Resource You can use any PLL resource.
    Reference Clock Mode External or Core.
    Feedback Mode Core. CLKOUT 1 to 3 from the PLL can be used for the feedback as long as the frequency and phase shift can be generated.
    Reference Clock Frequency User defined.
    Output Clocks mipi_clk—Frequency defined in MIPI IP core, phase shift 0°1
    SLOWCLK—Frequency is 1/8 the PHY speed, phase shift 0°, enable feedback.
    FASTCLK_D—Frequency is the speed you are running the PHY, phase shift 90.00°
    FASTCLK_C—Frequency is the speed you are running the PHY, phase shift 180.00°
    For example, if the PHY is running at 1,000 Mbps, FASTCLK_D and FASTCLK_C will run at half that 500 MHz (because it transfers data on both clock edges), and SLOWCLK will run at 125 MHz.
    Locked Pin Turn on
  2. Add a GPIO block with these settings to provide the reference clock input to the PLL:
    OptionDescription
    Mode Input
    Pin Name Any
    Connection Type pll_clkin
    GPIO Resource Assign the dedicated PLL_CLKIN pin that corresponds to the PLL you chose.
  3. Add MIPI TX Lane block with these settings:
    OptionDescription
    Mode data lane
    Parallel Clock Pin Name Name you are using for SLOWCLK.
    Serial Clock Pin Name Name you are using for FASTCLK_D.
  4. Repeat step 3 for each MIPI TX data lane you want to implement.
  5. Add another MIPI TX Lane block for the clock lane:
    OptionDescription
    Mode clock lane
    Parallel Clock Pin Name Name you are using for FASTCLK_D.
    Serial Clock Pin Name Name you are using for FASTCLK_C.
  6. Implement the rest of the MIPI TX interface in RTL using a MIPI TX IP core (CSI-2, D-PHY, or DSI). Refer to the user guide for the IP core for instructions.
1 This PLL also generates the mipi_clk, which is used in the MIPI IP core. Refer to the user guide for the IP core for details.