PCI Express Pins Tab

This tab has several sub-tabs for defining the PCI Express pins. Refer to "Interface Signals" in the Titanium PCIe® Controller User Guide for a complete definition of the pins and their function.

Table 1. Pins Tab: AXI Sub-Tab Settings

Parameter	Selection	Notes
Enable AXI Master Interface	On, off	Default: on. Indicate whether to use the AXI master.
Enable AXI Slave Interface	On, off	Default: on. Indicate whether to use the AXI slave.
AXI Clock Pin Name	User defined	Specify the pin name.
Invert AXI Clock Pin	On, off	Default: off. Indicate whether to invert the clock signal.
AXI Reset (Active-Low) Pin Name	User defined	Efinix recommends using the default names.
Master and slave tabs	User defined	These tabs define the pin names for the master and slave read/write data and address channels and sideband channel. Efinix recommends using the default names.

Table 2. Pins Tab: Interrupt Sub-Tab Settings

Parameter	Selection	Notes
Enable Interrupt	On, off	Default: off. Indicate whether to use the interrupt.
Interrupt Sideband Signals [27:0] Bus Name	User defined	Efinix recommends using the default names.
Local Error and Status Register Interrupt Pin name	User defined	Efinix recommends using the default names.
Legacy Interrupt tab	User defined	This tab defines the legacy interrupt pin names. Efinix recommends using the default names.
MSI tab	User defined	Available only when endpoint is selected. This tab defines the MSI pin names. To enable the MSI pins, turn on Enable MSI. Efinix recommends using the default names. MSI is not available in root port mode.

Table 3. Pins Tab: Message Sub-Tab Settings

Parameter	Selection	Notes
All	User defined	Define the pin names for the PCIe message interface. Efinix recommends using the default names.

Table 4. Pins Tab: Error Indication Sub-Tab Settings

Parameter	Selection	Notes
All	User defined	Define the pin names for the PCIe error interface. Efinix recommends using the default names.

Table 5. Pins Tab: APB Sub-Tab Settings

Parameter	Selection	Notes
APB Interface Clock Pin Name	User defined	Specify the pin name. The APB clock is required when using the PCI Express block for the PCIe Controller to enumerate successfully. The clock can be from an external source (through a GPIO) or from a PLL, If the clock comes from a PLL, the PLL must be configured in local feedback mode.
Invert APB Interface Clock Pin	On, off	Default: off. Indicate whether to invert the clock signal.
Pin and bus names	User defined	These fields define the APB interface pin names. Efinix recommends using the default names.

Table 6. Pins Tab: Hot Plug Sub-Tab Settings

Parameter	Selection	Notes
Hot Plug Interrupt Pin Name	User defined	Specify the name of the interrupt pin for hot plug events. Turn on the Slot Capability menu > Hot-plug Capable option to enable the Hot Plub tab.

Table 7. Pins Tab: Function Level Reset Sub-Tab Settings

Parameter	Selection	Notes
All	User defined	Define the pin names for the PCIe FLR interface. Efinix recommends using the default names.

Table 8. Pins Tab: Status Sub-Tab Settings

Parameter	Selection	Notes
Enable Status	On, off	Default: on. Indicate whether to use the PCIe status signals.
Pin and bus names	User defined	These fields define the PCIe status pin names. Efinix recommends using the default names.

Table 9. Pins Tab: Configuration Snoop Sub-Tab Settings

Parameter	Selection	Notes
Enable Configuration Snoop	On, off	Default: on. Indicate whether to use the PCIe configuration snoop signals.
Pin and bus names	User defined	These fields define the configuration snoop pin names. Efinix recommends using the default names.

Table 10. Pins Tab: Power Management Sub-Tab Settings

Parameter	Selection	Notes
Enable Power Management	On, off	Default: off. Indicate whether to use power management.
ASPM L1.1 Substate Enable	On, off	In root port mode, choosing L0s and L1 Entry or L1 Entry activates these options. Default: on
ASPM L1.2 Substate Enable	On, off
PM L1.1 Substate Enable	On, off	Default: off. Indicate whether to use PM L1.1 substate.
PM L1.2 Substate Enable	On, off	Default: off. Indicate whether to use the PM L1.2 substate.
ASPM Enable	Disabled L0s Entry L0s and L1 Entry L1 Entry	Choose the type of active state power management (ASPM) to use.
Power Management Clock Pin Name	User defined	Specify the pin name.
Power Management Clock Connection Type	rclk, gclk	Choose whether to use a global clock (gclk) or regional clock (rclk) for the power management clock pin.
Pin and bus names	User defined	These fields define the power management pin names. Efinix recommends using the default names.
L1 Substate tab pin and bus names	User defined	These pins are used when the ASPM L1.1, ASPM L1.2, PM L1.1, or PM L1.2 substates are enabled. Efinix recommends using the default names.