About the HSIO Interface

Each HSIO block uses a pair of I/O pins as one of the following:

  • Single-ended HSIO—Two single-ended I/O pins (LVCMOS, SSTL, HSTL)
  • Differential HSIO—One differential I/O pins:
    • Differential SSTL and HSTL
    • LVDS—Receiver (RX), transmitter (TX), or bidirectional (RX/TX)
    • MIPI lane I/O—Receiver (RX) or transmitter (TX)

Figure 1. HSIO Buffer Block Diagram
Important: When you are using an HSIO pin as a GPIO, make sure to leave at least one pair of unassigned HSIO pins between any GPIO and LVDS or MIPI lane pins. This rule applies for pins on each side of the device (top, bottom, left, right). This separation reduces noise. The Efinity software issues a warning if you do not leave this separation.