MIPI TX D-PHY

The MIPI TX D-PHY is a transmitter interface designed to transmit data and the control information of MIPI CSI, DSI, or other associated protocols. The MIPI TX D-PHY comprises of one clock lane and up to four data lanes for a single-channel configuration. The MIPI TX D-PHY also interfaces with MIPI-associated protocol controllers via a standard MIPI D-PHY PPI that supports the 8- or 16-bit high-speed receiving data bus.

Figure 1. MIPI TX D-PHY x4 Block Diagram

The MIPI TX D-PHY block requires an escape clock (TX_CLK_ESC) for use when the MIPI interface is in escape (low-power) mode, which runs up to 20 MHz.

Note: Efinix recommends that you set the escape clock frequency as close to 20 MHz as possible.

Figure 2. MIPI TX D-PHY Interface Block Diagram
Note: GPIO block is the default reference clock source. However, the PLL and core clock out can also be set as the reference clock source.
Table 1. MIPI TX D-PHY Clocks Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
REF_CLK Input N/A Reference Clock. The clock must be between 12 MHz to 52 MHz.
TX_CLK_ESC Input N/A Escape Mode Transmit Clock, used to generate escape sequence. The clock must be less than 20 MHz.
RX_CLK_ESC Output N/A Escape Mode Receive Clock (lane 0 only)
WORD_CLKOUT_HS Output N/A HS Transmit Byte/Word Clock. This signal must be 1/8 of the bit-rate in normal 8-bit HS-PPI D-PHY mode, or 1/16 of the bit-rate in 16-bit PHY mode.
Table 2. MIPI TX D-PHY Control and Status Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
RESET_N Input N/A Reset. Disables PHY and reset the digital logic.
PLL_UNLOCK Output N/A PLL is in unlock state.
PLL_SSC_EN Input N/A (Optional) PLL SSC Enable:
Always enable: 1
Disable: 0
Driven by active signal for dynamic enable
STOPSTATE_CLK Output N/A Clock Lane in Stop State (Clk 0).
TX_REQUEST_ESC_LANn Input TX_CLK_ESC Escape Mode Transmit Request (Lane N).
STOPSTATE_LANn Output N/A Data Lane in Stop State (Lane N).

Table 3. MIPI TX D-PHY Lane 0 Control and Status Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
TURN_REQUEST Input TX_CLK_ESC Lane 0 Turnaround Request.
TX_TRIGGER_ESC [3:0] Input TX_CLK_ESC Lane 0 Send an Escape Mode Trigger Event.
RX_TRIGGER_ESC [3:0] Output RX_CLK_ESC Lane 0 Received an Escape Mode Trigger Event.
FORCE_RX_MODE Input N/A Lane 0 Force into Receive Mode/Wait for Stop.
DIRECTION Output N/A Lane 0 Transmit/Receive Direction:
0: TX,
1: RX
ERR_ESC Output N/A Lane 0 Escape Command Error.
ERR_CONTROL Output N/A Lane 0 Line State Error.
ERR_CONTENTION_LP0 Output N/A Lane 0 Line Contention Detected (when driving 0).
ERR_CONTENTION_LP1 Output N/A Lane 0 Line Contention Detected (when driving 1).
Table 4. MIPI TX D-PHY High Speed Mode Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
TX_REQUEST_HS Input WORD_CLKOUT_HS HS Clock Request (Clk 0).
TX_REQUEST_HS_LANn Input WORD_CLKOUT_HS HS Transmit Request and Data Valid (Lane 0-3).
TX_SKEW_CAL_HS_LANn Input WORD_CLKOUT_HS HS Skew Calibration (Lane N).
TX_WORD_VALID_HS_LANn Input WORD_CLKOUT_HS HS High Byte Valid (Lane N) for 16-bit mode.
TX_DATA_HS_LANn [15:0] Input WORD_CLKOUT_HS HS Transmit Data (Lane N).
TX_READY_HS_LANn Output WORD_CLKOUT_HS HS Transmit Ready (Lane N).
Table 5. MIPI TX D-PHY Low-Power Data Receive Mode Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
TX_LPDT_ESC Input TX_CLK_ESC Lane 0 Enter LPDT Mode.
TX_VALID_ESC Input TX_CLK_ESC Lane 0 LPDT Data Valid .
TX_DATA_ESC [7:0] Input TX_CLK_ESC Lane 0 LPDT Data Bus.
TX_READY_ESC Output TX_CLK_ESC Lane 0 LPDT Data Ready.
RX_LDPT_ESC Output RX_CLK_ESC Escape LP Data Receive Mode.
RX_DATA _ESC[7:0] Output RX_CLK_ESC Escape Mode Receive Data.
RX_VALID_ESC Output RX_CLK_ESC Escape Mode Receive Data Valid.
ERR_SYNC_ESC Output N/A LPDT Data Sync Error.
RX_ULPS_ESC Output RX_CLK_ESC Lane 0 entered ULPS mode.
Table 6. MIPI TX D-PHY ULP Sleep Mode (Interface to FPGA Fabric)
Signal Direction Clock Domain Notes
TX_ULPS_CLK Input TX_CLK_ESC CLK0 to enter Ultra-Low Power State.
TX_ULPS_EXIT Input TX_CLK_ESC CLK0 to exit Ultra-Low Power State.
TX_ULPS_ACTIVE_CLK_NOT Output N/A Clock Lane in ULP State - Active Low (Clk 0).
TX_ULPS_ESC_LANn Input TX_CLK_ESC Lane n to enter Ultra-Low Power State.
TX_ULPS_EXIT_LANn Input TX_CLK_ESC Lane n to exit Ultra-Low Power State.
TX_ULPS_ACTIVE_NOT_LANn Output N/A Data Lane in ULP State - Active Low (Lane N).
Table 7. MIPI TX D-PHY Pads
Pad Direction Description
MIPIn_TXDP[4:0] Bidirectional MIPI transceiver P pads.
MIPIn_TXDN[4:0] Bidirectional MIPI transceiver N pads.