PCI Express Base Tab

In the Block Editor > Base tab you choose the resource and specify high level settings.

Table 1. Base Tab Settings
Parameter Choices Notes
Instance Name User defined Specify the instance name
PCIe Resource None, QUAD_0, QUAD_2 Choose the resource. QUAD_0 and QUAD_2 support PCIe.
Mode Endpoint, Root Port Choose whether the instance is an endpoint or root port.
In v2024.1, the PCIe root port has limited functionality.
Link Width x1, x2, x4 Choose the width.
Generation
Gen1 (2.5 Gbps)
Gen2 (5.0 Gbps)
Gen3 (8.0 Gbps)
Gen4 (max 16.0 Gbps)
 Choose the generation (and resulting speed).
Maximum Payload Size 128 bytes
256 bytes
512 bytes
 Choose the payload size.
Gen3 Equalization RX Preset User defined Root port only. Default: 0x3
Gen3 Equalization TX Preset User defined Root port only. Default: 0x3
Gen4 Equalization TX Preset User defined Root port only. Default: 0x2
Reference Clock Frequency User defined Specify the frequency
Reference Clock Source External Defaults to external.
External Clock > Clock CMN_REFCLK0 Defaults to CMN_REFCLK0. Block Editor shows the name of the resource that you should use for this clock.
Enable 50 Ω to ground on-die termination for REFCLK0 On, off Default: on. Use termination for the reference clock.
Reference clock from on-board crystal On, off Default: on. Use a crystal on the board as the PCIe reference clock instead of a signal from the edge card connector.
If you turn this option off, you need to create a PLL instance with:
  • BR0 or BR1 as the PLL resource
  • CLKOUT4 output clock enabled
  • An external reference clock resource (GPIOR_140 for BR0 or GPIOR_141 for BR1)
  • Local feedback mode
This PLL provides the temporary PCIe reference clock while the PHY is configuring. When the PHY completes configuration, the reference clock reverts to the edge card connector.