HSIO Configured as MIPI Lane

You can configure the HSIO block as a MIPI RX or TX lane. The block supports bidirectional data lane, unidirectional data lane, and unidirectional clock lane which can run at speeds up to 1.3 Gbps. The MIPI lane operates in high-speed (HS) and low-power (LP) modes. In HS mode, the HSIO block transmits or receives data with x8 serializer/deserializer. In LP mode, it transmits or receives data without deserializer/serializer.

The MIPI D-PHY standard is a point-to-point protocol with one endpoint (TX) responsible for initiating and controlling communication. Often, the standard is unidirectional, but when implementing the MIPI DSI protocol, you can use one TX data lane for LP bidirectional communication.

The protocol is source synchronous with one clock lane and 1, 2, 4, or 8 data lanes. The number of lanes available depends on which package you are using. A dedicated HSIO block is assigned on the RX interface as a clock lane while the clock lane for TX interface can use any of the HSIO block in the group.

MIPI RX Lane

In RX mode, the HS (fast) clock comes in on the MIPI clock lane and is divided down to generate the slow clock. The fast and slow clocks are then passed to neighboring HSIO blocks to be used for the MIPI data lanes.

The data lane fast and slow clocks must be driven by a clock lane in the same MIPI group (dedicated buses drive from the clock lane to the neighboring data lanes).

The MIPI RX function is defined as:

Table 1. MIPI RX Function

MIPI RX Function	Description
RX_DATA_xy_zz	MIPI RX Data Lane. You can use any data lanes within the same group to form multiple lanes of MIPI RX channel. x = P or N y = 0 to 7 data lanes (Up to 8 data lanes per channel) Tz50 zz = I0 to I11 MIPI RX channel (Up to 12 MIPI RX channels) Tz110, Tz170 zz = I0 to I17 MIPI RX channel (Up to 18 MIPI RX channels)
RX_CLK_x_zz	MIPI RX Clock Lane. One clock lane is required for each MIPI RX channel. x = P or N Tz50 zz = I0 to I11 MIPI RX channel (Up to 12 MIPI RX channels) Tz110, Tz170 zz = I0 to I17 MIPI RX channel (Up to 18 MIPI RX channels)

Notice: Refer to the pinout file for your FPGA for more information about the MIPI RX function for each HSIO and for which pins are in the same MIPI group.

Table 2. MIPI RX Lane Signals Interface to MIPI soft CSI/DSI controller with D-PHY in FPGA Fabric

Signal	Direction	Clock Domain	Description
LP_P_OE	Input	–	(Optional) LP output enable signal for P pad.
LP_P_OUT	Input	–	(Optional) LP output data from the core for the P pad. Used if the data lane is reversible.
LP_P_IN	Output	–	LP input data from the P pad.
CLKOUT	Output	–	Divided down parallel (slow) clock from the pads that can drive the core clock tree. Used to drive the core logic implementing the rest of the D-PHY protocol. It should also connect to the FIFOCLK of the data lanes.
SLOWCLKOUT1	Output	–	Divided down parallel (slow) clock from the pads. Can only drive RX DATA lanes.
FASTCLKOUT1	Output	–	Serial (fast) clock from the pads. Can only drive RX DATA lanes.
HS_IN[7:0]	Output	SLOWCLK	High-speed parallel data input.
FIFO_EMPTY	Output	FIFOCLK	(Optional) When the FIFO is enabled, this signal indicates that the FIFO is empty.
FIFO_RD	Input	FIFOCLK	(Optional) Enables FIFO to read.
RST	Input	FIFOCLK SLOWCLK	(Optional) Asynchronous. Resets the FIFO and serializer. If the FIFO is enabled, it is relative to FIFOCLK; otherwise it is relative to SLOWCLK.
FIFOCLK1	Input	–	(Optional) Core clock to read from the FIFO.
SLOWCLK1	Input	–	Parallel (slow) clock.
FASTCLK1	Input	–	Serial (fast) clock.
DLY_INC	Input	SLOWCLK	(Optional) Dynamic delay control. When DLY_ENA is 1, 1: Increments 0: Decrements
DLY_ENA	Input	SLOWCLK	(Optional) Enable the dynamic delay control.
DLY_RST	Input	SLOWCLK	(Optional) Reset the delay counter.
LP_N_OE	Input	–	(Optional) LP output enable signal for N pad.
LP_N_OUT	Input	–	(Optional) LP output data from the core for the N pad. Used if the data lane is reversible.
LP_N_IN	Output	–	LP input data from the N pad.
HS_ENA	Input	–	Dynamically enable the differential input buffer when in high-speed mode.
HS_TERM	Input	–	Dynamically enables input termination high-speed mode.

The clock lane generates the fast clock and slow clock for the RX data lanes within the interface group. It also generates a clock which is divided by 4 that feeds the global network. The following figure shows the clock connections between the clock and data lanes.

MIPI TX Lane

In TX mode, a PLL generates the parallel and serial clocks and passes them to the clock and data lanes.

Table 3. MIPI TX Lane Signals Interface to MIPI soft CSI/DSI controller with D-PHY in FPGA fabric

Signal	Direction	Clock Domain	Description
LP_P_OE	Input	–	LP output enable signal for P pad.
LP_P_OUT	Input	–	LP output data from the core for the P pad.
LP_P_IN	Output	–	(Optional) LP input data from the P pad. Used if data lane is reversible.
HS_OE	Input	–	High-speed output enable signal.
RST	Input	SLOWCLK	(Optional) Resets the serializer.
HS_OUT[7:0]	Input	SLOWCLK	High-speed output data from the core. Always 8-bits wide.
SLOWCLK	Input	–	Parallel (slow) clock.
FASTCLK	Input	–	Serial (fast) clock.
LP_N_OE	Input	–	LP output enable signal for N pad.
LP_N_OUT	Input	–	LP output data from the core for the N pad.
LP_N_IN	Output	–	(Optional) LP input data from the N pad. Used if data lane is reversible.