Interface Blocks

Topaz™ FPGAs support a variety of interface blocks. The available blocks differ depending on which FPGA you target and the package. You need to assign a resource for every block you use.

The following table describes the interface blocks supported in the Efinity® software.

Note: New package support is often added in patches. Refer to the Efinity Release Notes in the Support Center for the latest patch support.
Table 1. Topaz Interface Block Support by Package
Interface Tz50 Tz75 Tz100 Tz110 Tz170 Tz200 Tz325
DDR – All All J361, J484 J361, J484 C529 C529
GPIO All All All All All All All
GPIO bus All All All All All All All
I/O bank All All All All All All All
JTAG User TAP All All All All All All All
LVDS TX
LVDS RX
Bidirectional LVDS
 All All All All All All All
MIPI DPHY – All All J361, J484 J361, J484 N484, N900 N484, N900
MIPI TX Lane
MIPI RX Lane
 All All All All All All All
PCI Express®
Ethernet XGMII
Ethernet SGMII
PMA Direct
 – All All – – N484, N900 N484, N900
PLL (V3) All – – All All – –
PLL (Fractional) – All All – – All All
PLL SSC – All All J361, J484 J361, J484 N484, N900 N484, N900
Oscillator All All All All All All All
Quad-Core RISC-V – All All – – All All

All interface blocks have an instance name that must be a unique identifier. When you add a new block, the Interface Designer gives the block a unique default name, which you can change.

Note: After you re-name the block, press Enter or click Save to save the name.

Pin names are the top-level ports of the design implemented in the core that connect to the interface block. These names must be legal Verilog HDL or VHDL identifiers.