Using the GPIO Block

This block defines the functionality of the general-purpose I/O (GPIO) pins. The mode you select determines the GPIO capabilities and which settings you can configure. GPIO modes are: input, output, inout, clkout, and none.

You can assign GPIO to HVIO or HSIO resources. These resources support different I/O standards and have different features. When you check the interface design, the software compares your selections to the resource you assigned to the GPIO block. If the resource does not support your selection(s), the software reports it.

Create a GPIO

To create a new GPIO block, select GPIO in the Design Explorer and then click the Create Block button.

  1. Specify the instance name.
  2. Choose the Mode (input, output, inout, clkout, or none).
  3. Set the options as described in the following sections.
  4. Assign a resource for the signal using the Resource Assigner.
Note: You can set the default state of unused GPIO. Click the GPIO(n) category under Design Explorer. In the Block Editor to the right, select the unused state (input with weak pull up or input with weak pull down).
Note: When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO pins between any GPIO and HSIO pins in the same bank. This separation reduces noise. The Efinity software issues an error if you do not leave this separation.

Input Mode

Use input mode for input signals.

Table 1. Input Mode Options
Option Choices Description
Connection Type
normal, gclk, pll_clkin, pll_extfb, mipi_clkin, pcie_perstn,1 rclk, vref
 Some pins have alternate functions, and you use this option to choose the function. (This option only applies to pins that have alternate functions. Refer to the data sheet for your for pin information.) For example, a PLL can use a GPIO with an alternate connection type as a reference clock.
Note: If you set the connection type to pll_clkin or mipi_clkin, the signal is also available as a regular input to the core.
Register Option register, none Choose whether the input is registered.
If you choose register:
  • Define an input clock pin name.
  • Turn clock inversion on or off.
  • Under Double Data I/O Option, select one of the following:
    none Do not use double data I/O.
    normal Data is passed to the core on both the positive and negative clock edges
    resync Data is resynchronized to pass both data signals on the positive clock edge. <pin name>_hi is the positive edge and <pin name>_lo is the negative edge.
    pipeline Similar to resync except the data for both signals starts on the same clock edge.
  • To use the deserializer, turn on Enable Deserialization and specify the serial clock pin name. (You cannot use the deserializer with DDIO.)
Pull Option none, weak pullup, weak pulldown, dynamic Specify if you want a pull option.
If you choose dynamic, you must also specify the Dynamic Pull Up Enable Pin Name.
Enable Schmitt Trigger On or off Optionally enable a Schmitt trigger.
Enable Bus Hold On or off Optionally enable a bus hold.
Static Delay Settting Integer 0-15 For single-ended only. Choose the amount of static delay, each step adds approximately 60 ps of delay.
You can only set the static delay for individual signals, not buses.
0 - 63 For differential only: 64 steps with approximately 25 ps of delay per step.
You cannot use the static delay and dynamic delay simultaneously.
Enable Dynamic Delay On or off For inputs, 64 steps with approximately 25 ps of delay per step. If you enable this option, specify the enable, reset, and control pins as well as the clock pin.
You can ony set the dynamic delay for individual signals, not buses.
A clock is required when using the dynamic delay. If the input register is used, the clock is the same as the input register. Otherwise, you have to define a clock in the dynamic delay group box.
The delay is updated on the rising clock edge of DLYCLK.

Output Mode

Use output mode for output signals.

Table 2. Output Mode Options
Option Choices Description
Constant Output none, 1, 0 Choose whether the output is VCC (1) or GND (0). Otherwise, leave this option as none.
Register Option none, register, inv_register Choose whether the output is registered or has an inverted register.
If you choose register:
  • Define an output clock pin name.
  • Turn clock inversion on or off.
  • Under Double Data I/O Option, select one of the following:
    none Do not use double data I/O.
    normal Data is passed to the core on both the positive and negative clock edges
    resync Data is resynchronized to pass both data signals on the positive clock edge. <pin name>_hi is the positive edge and <pin name>_lo is the negative edge.
  • To use the serializer, turn on Enable Serialization and specify the serial clock pin name. (You cannot use the serializer with DDIO.)
The invert register option (inv_register) does not support DDIO.
Drive Strength Depends on I/O standard Choose the drive strength current in mA.
The HVIO and HSIO have different drive strength options depending on the I/O standard you choose. If you change the I/O standard, the Interface Designer resets the drive strength setting if the value is out of range for the selected standard.
Enable Fast Slew Rate On or off Optionally enable slew rate.
Static Delay Settting 0 - 63 Choose the amount of static delay, each step adds approximately 60 ps of delay.
You can only set the static delay for individual signals, not buses.

Inout Mode

Use inout mode for bidirectional signals. Inout mode has the same options for the input and output as the input and output modes.

Inout mode also has an output enable signal (optionally registered) to enable or disable the output buffer. The pin name you specify should be the same as the one you use in your RTL design. Setting the output enable signal to high (“1”) in your RTL design enables the output buffer.

Notice: For information on how to create a tri-state buffer, refer to “How do I create a Tri-State Buffer" in the Support Center Knowledgebase.

Clock Output Mode

Use clkout mode for clock output signals. You do not need to name the pin, but you do need to specify the output clock Pin Name.

None

Use none for unused signals. Specify whether the unused signal should have a weak pullup (default) or pulldown.

1 Only available for FPGAs with transceivers.