Create a RX Deserializer Interface

About this task

The following figure shows a completed RX deserializer interface, the deserialization width is 4 and m is the number of RX lanes.

Figure 1. Complete RX ISerializer nterface Block Diagram

Follow these steps to build this interface using the Efinity® Interface Designer.

Procedure

  1. Add a PLL block with the following settings:
    OptionDescription
    Resource You can use any PLL resource.
    Reference Clock Mode Any
    Reference Clock Frequency Any
    Output Clock Define the output clocks so that you have one for the fast clock (serial) and one for the slow clock (parallel).
    The fast clock (INFASTCLK) should be 4 times faster than the slow clock (INCLK). . The serial clock phase shift should be between 45 and 135 degrees.
  2. Add a GPIO block with these settings to provide the reference clock input to the PLL:
    OptionDescription
    Mode Input
    Pin Name Any
    Connection Type pll_clkin
    GPIO Resource Assign the dedicated PLL_CLKIN pin that corresponds to the PLL you chose.
  3. Add a GPIO block with these settings:
    OptionDescription
    Mode input
    Register Option register
    Enable Serialization Turn on
    Clock Pin Name Use the slow clock output name that corresponds to the PLL you chose.
    Serial Clock Pin Name Use the fast clock output name that corresponds to the PLL you chose.
  4. Repeat step 3 for each RX deserializer you want to implement.