PLL Interface
Efinix FPGAs have one or more PLLs to generate clock frequencies. The number of PLLs and the PLL features vary depending on the family and FPGA.
| PLL Version | Description | Available In |
|---|---|---|
| PLL V3 | Full-featured PLL | Topaz Tz50, Tz110, and Tz170 FPGAs. |
| FPLL V1 | Fractional PLL | Topaz Tz75, Tz100, Tz200, and Tz325 FPGAs. |
| PLL SSC | Spread-spectrum clocking PLL | Topaz FPGAs that have a hardened MIPI D-PHY interface. |
Note: Vx refers to the version number. This number is used to reference the PLL in
the Efinity Python API and interface primitives.