PLL Timing and AC Characteristics
The following tables describe the PLL timing and AC characteristics.
| Symbol | Parameter | Min | Typ | Max | Units |
|---|---|---|---|---|---|
| FIN | Input clock frequency. | 16 | – | 800 | MHz |
| FOUT | Output clock frequency. | 0.1342 | – | 1,000 | MHz |
| FVCO | PLL VCO frequency. | 2,200 | – | 5,500 | MHz |
| FPLL | Post-divider PLL VCO frequency. | – | – | 4,000 | MHz |
| FPFD | Phase frequency detector input frequency. | 16 | – | 800 | MHz |
| Symbol | Parameter | Min | Typ | Max | Units |
|---|---|---|---|---|---|
| tDT | Output clock duty cycle. | 45 | 50 | 55 | % |
| tOPJIT | Output clock period jitter
(PK-PK). This
specification applies when an input jitter of 20 ps is
applied. |
– | – | 200 | ps |
| tOPJITN | Output clock period jitter (PK-PK) with noisy
input. This
specification applies for a maximum allowed input jitter of 800
ps. The period jitter is measured over 10,000 sample size
with minimal core and I/O activity. |
– | – | 400 | ps |
| tOPJITFRAC | Output clock period jitter for fractional mode (PK-PK). | – | – | 650 | ps |
| tOPJITNFRAC | Output clock period jitter for fractional mode with noisy input (PK-PL). | – | – | 850 | ps |
| tINDT | Input duty clock cycle. | 45??? | – | 55??? | % |
| tILJIT | Input clock long-term jitter (PK-PK). | – | – | 800 | ps |
| tPLL_HLW | PLL input clock high/low pulse width. | 0.56 | – | – | ns |
| tLOCK | PLL lock-in time. | – | 300 | 600 | PFD1 |
1 The
PFD
cycle
is
equal
to
the
reference clock
divider
divided
by
the reference clock frequency.