Design Check: PLL Messages

Note: These design rules are also applicable to fractional PLL blocks.

When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error messages you may encounter and explains how to fix them.

pll_rule_clksel_pin (error)

Message	Valid characters are alphanumeric characters with dash and underscore only.
To fix	Update the pin name for the clock selector pin when reference clock mode is dynamic

pll_rule_dynamic_shift_invalid_pin (error)

Message	Invalid pin names found: <pin names>
To fix	Specify a valid pin name.

pll_rule_dynamic_shift_feedback (error)

Message	Output clock <name> used as feedback cannot be set with dynamic phase shift
To fix	If you are using a PLL output clock for feedback, you cannot use dynamic phase shifting. Instead, specify a phase.

pll_rule_dynamic_shift_empty_pin (error)

Message	Dynamic phase shift is enabled but missing pin names: <list>
To fix	For a PLL output, if you are turn on Dynamic for the phase shift, you also need to specify names for the SHIFT, SHIFT_SELECT, and SHIFT_ENA pins.

pll_rule_extfb_io (error)

Message	External feedback and reference clock have to be of the same instance type and IO standard
To fix	Use the same I/O standard for the external feedback clock and reference clock GPIO blocks.

pll_rule_extfb_resource (error)

Message	There can only be one configured resource for external IO feedback
To fix	In external feedback mode, you can only specify one clock out pin for feedback.

Message	External IO feedback resource <name> is not configured as pll_extfb connection
To fix	In the GPIO block that is your feedback resource, set the Connection Type to pll_extfb.

Message	The resource for external IO feedback is not configured
To fix	Add a GPIO block in input mode, set the Connection Type to pll_extfb, and assign it to a resource that supports the pll_extb connection type.

Message	External IO feedback resource is unbonded
To fix	Use a resource that is available in the device for external I/O feedback.

pll_rule_fb_freq (error)

Message	Feedback frequency <#>MHz is out of range. Min=<>MHz Max=<>MHz
To fix	The feedback frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_feedback_clock (error)

Message	Feedback clock name is required with non-internal feedback
To fix	You need to specify a clock pin name when you are not using internal feedback mode.

Message	Feedback clock name <string> is not from the same PLL
To fix	You need to use one of the output clocks from the PLL you are configuring as the feedback clock. You cannot use an output clock from a different PLL.

Message	Feedback clock in local mode has to connect to output clock 0
To fix	When Feedback Mode is Local, you can only use output clock 0 for feedback.

Message	Feedback clock <string> is not connected to pll clkout
To fix	The feedback clock you are using needs to be one of the output clocks from the PLL.

pll_rule_feedback_clock (info)

Message	Feedback clock phase shift is not 0-degree, check that the feedback clock is in-phase with the reference clock.
To fix	Set the feedback clock phase to 0 degrees in the PLL Clock Calculator. Efinix recommends a 0 degree phase for feedback clocks.

pll_rule_feedback_clk_regional (error)

Message	Unroutable regional clock output 4 to the core feedback interface with external reference clock resource set to <resource name>. Select a different reference clock resource or assign a different output clock as feedback clock.
To fix	This error only applies to Tz50 FPGAs. Use a different I/O resource as the external reference clock or use a different output clock as the feedback clock.

pll_rule_feedback_mode (error)

Message	Internal feedback mode is not supported
To fix	You may receive this error when configuring an interface with the API. Do not use internal feedback mode as it's not supported.

pll_rule_input_freq (error)

Message	Input Frequency <float> MHz (after pre-divider) is out of range. Min=<float>MHz Max=<float>MHz
To fix	Assign the reference clock frequency to a value within the specified range.

pll_rule_input_freq_limit (error)

Message	Input Frequency <float> MHz is out of range. Min=<float>MHz Max=<float>MHz
To fix	Assign the right reference clock frequency.

pll_rule_inst_name (error)

Message	Instance name is empty Valid characters are alphanumeric characters with dash and underscore only
To fix	Specify a valid instance name.

pll_rule_mipi_tx_clock (error)

Message	PLL output clock <name> is not allowed to connect to MIPI TX Lane Serial and Parallel clocks at the same time
To fix	You cannot use the slow clock for one MIPI TX lane as the fast clock for a different MIPI TX lane.

pll_rule_multiplier (error)

Message	Multiplier is invalid. Valid values are <values>.
To fix	The multiplier frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_oc_cascade (warning)

Message	(O * C == 1), PLL cascading is not supported with possible PLL clkout: <clock names>
To fix	The listed PLL output clocks cannot be cascaded. Change your design so they are not cascaded.

pll_rule_out_clk_conn_type (error)

Message	<PLL resource> does not support regional clock connection on output clock #
To fix	Some FPGAs allow you to choose whether to connect output clocks 3 and 4 to the global or regional clock network. You get this error when the PLL you selected does not support the regional clock connection. Change the setting to use the global clock or use another PLL.

pll_rule_outclk_div_pshift (warning)

Message	Enable phase shift with odd output clock divider will result in duty cycle distortion on the output clock. It is not advisable to use the clock for double data operation: <output clock names>
To fix	You can ignore this warning message if you are not using the clock output for double data rates. If you are using double data rate, instead choose an even clock divider.

pll_rule_output_clock (error)

Message	At least one output clock must be configured
To fix	Configure at least one PLL output clock and specify the output clock pin name.

Message	Output clock count is out of range. Min=<int>Max=<int>
To fix	You have specified the wrong number of output clocks (too many or none).

pll_rule_output_divider (error)

Message	Output divider for <clock name> is invalid. Valid values are between 1-128
To fix	Choose a value between 1 and 128.

pll_rule_output_freq (error)

Message	Output frequency <float>MHz is out of range. Min=<float>MHz Max=<float>MHz
To fix	The output frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_output_name (error)

Message	PLL output clock names have to be unique. Duplicates found: <list of string>
To fix	You get this error when you use duplicate clock names. Rename them.

pll_rule_output_number (error)

Message	Output number for <clk name> is invalid. It must be between 0 to <int>
To fix	The output clocks are numbered (e.g., CLKOUT3). Make sure that the number is within specified range.

pll_rule_param (error)

Message	Invalid parameters configuration: <feature>
To fix	Performs a general check for invalid parameters. Review the other error messages.

pll_rule_pll_freq (error)

Message	PLL Frequency is out of range, Freq=<value> Min=<min>MHz Max=<max>MHz
To fix	The maximum post-divided VCO clock fmax is 4,000 Mhz. Change the PLL clock calculator settings so that it is in range.

pll_rule_post_divider (error)

Message	Post-divider is invalid. Valid values are <list of int>
To fix	Choose a post divider value from the list shown.

pll_rule_pre_divider (error)

Message	Pre-divider is out of range. Min=<int> Max=<int>
To fix	The pre-divider frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_refclk (error)

Message	Bonded external reference clock pin has to be specified in dynamic mode
To fix	When using dynamic as the Clock Source, the PLL expects to find the resource for the external clock(s). Add a GPIO block in input mode, set the Connection Type to pll_clkin, and assign it to the resource shown in the PLL Properties tab under Dynamic Clock.

Message	Both core refclk pins have to be specified in dynamic mode
To fix	When using dynamic as the Clock Source, you need to specify the names for the core clocks 0 and 1. (Some PLLs use 2 core clocks in dynamic mode.)

Message	Core refclk pin has to be specified in core mode
To fix	When using core as the Clock Source, you need to specify the pin name.

Message	Core refclk pin has to be specified in dynamic mode
To fix	When using dynamic as the Clock Source, you need to specify the names for core clock 0. (Some PLLs use only 1 core clock in dynamic mode.)

Message	External refclk pin has to be set in external mode
To fix	When using external as the Clock Source, the PLL expects to find the resource for the external clock. Add a GPIO block in input mode, set the Connection Type to pll_clkin, and assign it to the resource shown in the PLL Properties tab under External Clock.

Message	External reference clock resource {} is not configured as pll_clkin connection
To fix	You use a GPIO block configured in alternate connection mode to be the reference clock for the PLL. Change the GPIO Connection Type to pll_clkin.

Message	Reference clock at <resource> connected to external clock pin {0\|1\|2} has not been defined
To fix	The PLL expects to find the resource for the external clock. Add a GPIO block in input mode, set the Connection Type to pll_clkin, and assign it to the resource shown in the PLL Properties tab under External Clock.

Message	Invalid external clock {0\|1\|2} resource selected: Resource Unbonded
To fix	In the FPGA/package combination you are using, you cannot use the external clock resoure specified because it is not available in the package.

Message	The resource for CLKIN[<index>] is not configured
To fix	The PLL expects to find the resource for the PLL clockin. Add a GPIO block in input mode, set the Connection Type to pll_clkin, and assign it to the correct resource.

Message	There can only be one configured resource for CLKIN[<index>]
To fix	Each clock input can have only one resource. The software issues an internal error. Contact your local FAE for help.

pll_rule_resource (error)

Message	Resource name is empty Resource is not a valid PLL device instance
To fix	Choose a valid PLL resource.

pll_rule_vco_freq (error)

Message	VCO frequency is out of range. Freq=<float> Min=<float>MHz Max=<float>MHz
To fix	The VCO frequency needs to be within the range specified. Adjust the parameters to meet that requirement.