Important: All information is preliminary and pending
definition.
TopazFPGAs have a hardened RISC-V block with a 32-bit CPU featuring
the ISA RISCV32I with M, A, C, F, and D extensions, and six pipeline stages (fetch,
injector, decode, execute, memory, and writeback). The hard processor has four CPUs each
with a dedicated FPU and custom instructions. The processor supports the standard RISC-V
debug specification with eight hardware breakpoints as well as machine and supervisor
privileged mode, and Linux MMU SV32 page-based virtual memory.
Figure 1. Hardened RISC-V Block Overview
This topic provides an overview of the hardened RISC-V block and the signals that connect
to the Topaz's core fabric and interfaces. For complete details on
the processor and its specifications, refer to the Sapphire High-Performance RISC-V SoC Data Sheet.
Figure 2. Hardened RISC-V Block Diagram
The hardened RISC-V block is connected directly to port 1 on the hard LPDDR4 controller;
therefore, you do not need to implement those connections. Your design should implement
the other interface blocks as needed.
The PLLs that can feed the RISC-V system clock are BL0 CLKOUT1, BL1 CLKOUT2, or
BL2 CLKOUT1.
The PLLs that can feed the RISC-V memory clock are BL0 CLKOUT2, BL1 CLKOUT1, or
BL2 CLKOUT2.
Note: The PLL that clocks the hardened RISC-V block should not use fractional output
or spread-spectrum clocking because these features increase jitter.
AXI4 Slave Interface for Peripherals
The AXI slave interface connects to user-defined peripherals through an AXI
interconnect bus. You use the IP Manager to build the AXI interconnect and
peripherals.
Table 1. AXI Interrupt
Port
Direction
Clock Domain
AXIAINTERRUPT
Output
io_peripheralClk
Table 2. AXI Slave Read Address Channel
Port
Direction
Clock Domain
Description
AXIA_ARADDR[31:0]
Input
io_peripheralClk
Read address. It gives the address of the first
transfer in a burst transaction.
AXIA_ARBURST[1:0]
Input
io_peripheralClk
Burst type. The burst type and the size determine
how the address for each transfer within the burst is
calculated.
’b01 = INCR
’b10 = WRAP
AXIA_ARCACHE[3:0]
Input
io_peripheralClk
Memory type. This signal indicates how transactions are required
to progress through a system.
AXIA_ARLEN[7:0]
Input
io_peripheralClk
Burst length. This signal indicates the number of
transfers in a burst.
AXIA_ARLOCK
Input
io_peripheralClk
Lock type. This signal provides additional
information about the atomic characteristics of the
transfer.
AXIA_ARPROT[2:0]
Input
io_peripheralClk
Defines the access permissions for read accesses.
AXIA_ARQOS[3:0]
Input
io_peripheralClk
QoS identifier for read transaction.
AXIA_ARREADY
Output
io_peripheralClk
Address ready. This signal indicates that the slave
is ready to accept an address and associated control
signals.
AXIA_ARREGION[3:0]
Input
io_peripheralClk
Region identifier. Permits a single physical interface on a slave
to be used for multiple logical interfaces.
AXIA_ARSIZE[2:0]
Input
io_peripheralClk
Burst size. This signal indicates the size of each
transfer in the burst.
AXIA_ARVALID
Input
io_peripheralClk
Address valid. This signal indicates that the
channel is signaling valid address and control information.
Table 3. AXI Slave Write Address Channel
Port
Direction
Clock Domain
Description
AXIA_AWADDR[31:0]
Input
io_peripheralClk
Write address. It gives the address of the first
transfer in a burst transaction.
AXIA_AWBURST[1:0]
Input
io_peripheralClk
Burst type. The burst type and the size determine
how the address for each transfer within the burst is
calculated.
AXIA_AWCACHE[3:0]
Input
io_peripheralClk
Memory type. This signal indicates how transactions
are required to progress through a system.
AXIA_AWLEN[7:0]
Input
io_peripheralClk
Burst length. This signal indicates the number of
transfers in a burst.
AXIA_AWLOCK
Input
io_peripheralClk
Lock type. This signal provides additional
information about the atomic characteristics of the
transfer.
AXIA_AWPROT[2:0]
Input
io_peripheralClk
Defines the access permissions for write accesses.
AXIA_AWQOS[3:0]
Input
io_peripheralClk
QoS identifier for write transaction.
AXIA_AWREADY
Output
io_peripheralClk
Address ready. This signal indicates that the slave
is ready to accept an address and associated control
signals.
AXIA_AWREGION[3:0]
Input
io_peripheralClk
Region identifier. Permits a single physical interface on a slave
to be used for multiple logical interfaces.
AXIA_AWSIZE[2:0]
Input
io_peripheralClk
Burst size. This signal indicates the size of each
transfer in the burst.
AXIA_AWVALID
Input
io_peripheralClk
Address valid. This signal indicates that the
channel is signaling valid address and control information.
Table 4. AXI Slave Write Response Channel
Port
Direction
Clock Domain
Description
AXIA_BREADY
Input
io_peripheralClk
Response ready. This signal indicates that the master
can accept a write response.
AXIA_BRESP[1:0]
Output
io_peripheralClk
Read response. This signal indicates the status of the
read transfer.
AXIA_BVALID
Output
io_peripheralClk
Write response valid. This signal indicates that the
channel is signaling a valid write response.
Table 5. AXI Slave Read Data Channel
Port
Direction
Clock Domain
Description
AXIA_RDATA[31:0]
Output
io_peripheralClk
Read data.
AXIA_RLAST
Output
io_peripheralClk
Read last. This signal indicates the last transfer in
a read burst.
AXIA_RREADY
Input
io_peripheralClk
Read ready. This signal indicates that the master can
accept the read data and response information.
AXIA_RRESP[1:0]
Output
io_peripheralClk
Read response. This signal indicates the status of the
read transfer.
AXIA_RVALID
Output
io_peripheralClk
Read valid. This signal indicates that the channel is
signaling the required read data.
Table 6. AXI Slave Write Data Channel
Port
Direction
Clock Domain
Description
AXIA_WDATA[31:0]
Input
io_peripheralClk
Write data.
AXIA_WLAST
Input
io_peripheralClk
Write last. This signal indicates the last transfer in
a write burst.
AXIA_WREADY
Output
io_peripheralClk
Write ready. This signal indicates that the slave can
accept the write data.
AXIA_WSTRB[3:0]
Input
io_peripheralClk
Write strobes. This signal indicates which byte lanes
hold valid data. There is one write strobe bit for each eight bits
of the write data bus.
AXIA_WVALID
Input
io_peripheralClk
Write valid. This signal indicates that valid write
data and strobes are available.
AXI Interface to DMA
This AXI master interface has a 128-bit data channel to connect to the DMA controller
IP core.
Table 7. Clock and Reset
Port
Direction
Clock Domain
Description
IO_DDRMASTERS_0_CLK
Input
IO_DDRMASTERS_0_RESET
Input
IO_DDRMASTERS_0_CLK
Table 8. AXI Master Read Address Channel
Port
Direction
Clock Domain
Description
IO_DDRMASTERS_0_AR_PAYLOAD_ADDR[31:0]
Output
IO_DDRMASTERS_0_CLK
Read address. It gives the address of the first
transfer in a burst transaction.
IO_DDRMASTERS_0_AR_PAYLOAD_BURST[1:0]
Output
IO_DDRMASTERS_0_CLK
Burst type. The burst type and the size determine
how the address for each transfer within the burst is
calculated.
’b01 = INCR
’b10 = WRAP
IO_DDRMASTERS_0_AR_PAYLOAD_CACHE[3:0]
Output
IO_DDRMASTERS_0_CLK
Memory type. This signal indicates how transactions are required
to progress through a system.
IO_DDRMASTERS_0_AR_PAYLOAD_ID[3:0]
Output
IO_DDRMASTERS_0_CLK
Address ID. This signal identifies the group of address
signals.
IO_DDRMASTERS_0_AR_PAYLOAD_LEN[7:0]
Output
IO_DDRMASTERS_0_CLK
Burst length. This signal indicates the number of
transfers in a burst.
IO_DDRMASTERS_0_AR_PAYLOAD_LOCK
Output
IO_DDRMASTERS_0_CLK
Lock type. This signal provides additional
information about the atomic characteristics of the
transfer.
IO_DDRMASTERS_0_AR_PAYLOAD_PROT[2:0]
Output
IO_DDRMASTERS_0_CLK
Defines the access permissions for read accesses.
IO_DDRMASTERS_0_AR_PAYLOAD_QOS[3:0]
Output
IO_DDRMASTERS_0_CLK
QoS identifier for read transaction.
IO_DDRMASTERS_0_AR_PAYLOAD_REGION[3:0]
Output
IO_DDRMASTERS_0_CLK
Region identifier. Permits a single physical interface to be used
for multiple logical interfaces.
IO_DDRMASTERS_0_AR_PAYLOAD_SIZE[2:0]
Output
IO_DDRMASTERS_0_CLK
Burst size. This signal indicates the size of each
transfer in the burst.
IO_DDRMASTERS_0_AR_READY
Input
IO_DDRMASTERS_0_CLK
Address ready. This signal indicates that the slave
is ready to accept an address and associated control
signals.
IO_DDRMASTERS_0_AR_VALID
Output
IO_DDRMASTERS_0_CLK
Address valid. This signal indicates that the
channel is signaling valid address and control information.
Table 9. AXI Master Write Address Channel
Port
Direction
Clock Domain
Description
IO_DDRMASTERS_0_AW_VALID
Output
IO_DDRMASTERS_0_CLK
Address valid. This signal indicates that the
channel is signaling valid address and control information.
IO_DDRMASTERS_0_AW_READY
Input
IO_DDRMASTERS_0_CLK
Address ready. This signal indicates that the slave
is ready to accept an address and associated control
signals.
IO_DDRMASTERS_0_AW_PAYLOAD_ADDR[31:0]
Output
IO_DDRMASTERS_0_CLK
Write address. It gives the address of the first
transfer in a burst transaction.
IO_DDRMASTERS_0_AW_PAYLOAD_ID[3:0]
Output
IO_DDRMASTERS_0_CLK
Address ID. This signal identifies the group of address
signals.
IO_DDRMASTERS_0_AW_PAYLOAD_REGION[3:0]
Output
IO_DDRMASTERS_0_CLK
Region identifier. Permits a single physical interface to be used
for multiple logical interfaces.
IO_DDRMASTERS_0_AW_PAYLOAD_LEN[7:0]
Output
IO_DDRMASTERS_0_CLK
Burst length. This signal indicates the number of
transfers in a burst.
IO_DDRMASTERS_0_AW_PAYLOAD_SIZE[2:0]
Output
IO_DDRMASTERS_0_CLK
Burst size. This signal indicates the size of each
transfer in the burst.
IO_DDRMASTERS_0_AW_PAYLOAD_BURST[1:0]
Output
IO_DDRMASTERS_0_CLK
Burst type. The burst type and the size determine
how the address for each transfer within the burst is
calculated.
IO_DDRMASTERS_0_AW_PAYLOAD_LOCK
Output
IO_DDRMASTERS_0_CLK
Lock type. This signal provides additional
information about the atomic characteristics of the
transfer.
IO_DDRMASTERS_0_AW_PAYLOAD_CACHE[3:0]
Output
IO_DDRMASTERS_0_CLK
Memory type. This signal indicates how transactions
are required to progress through a system.
IO_DDRMASTERS_0_AW_PAYLOAD_QOS[3:0]
Output
IO_DDRMASTERS_0_CLK
QoS identifier for write transaction.
IO_DDRMASTERS_0_AW_PAYLOAD_PROT[2:0]
Output
IO_DDRMASTERS_0_CLK
Defines the access permissions for write accesses.
IO_DDRMASTERS_0_AW_PAYLOAD_ALLSTRB
Output
IO_DDRMASTERS_0_CLK
Write all strobes asserted. The DDR controller
only supports a maximum of 16 AXI beats for write commands using
this signal.
Table 10. AXI Master Write Response Channel
Port
Direction
Clock Domain
Description
IO_DDRMASTERS_0_B_PAYLOAD_ID[3:0]
Input
IO_DDRMASTERS_0_CLK
Response ID tag. This signal is the ID tag of the write
response.
IO_DDRMASTERS_0_B_PAYLOAD_RESP[1:0]
Input
IO_DDRMASTERS_0_CLK
Read response. This signal indicates the status of the
read transfer.
IO_DDRMASTERS_0_B_READY
Output
IO_DDRMASTERS_0_CLK
Response ready. This signal indicates that the master
can accept a write response.
IO_DDRMASTERS_0_B_VALID
Input
IO_DDRMASTERS_0_CLK
Write response valid. This signal indicates that the
channel is signaling a valid write response.
Table 11. AXI Master Read Data Channel
Port
Direction
Clock Domain
Description
IO_DDRMASTERS_0_R_PAYLOAD_DATA[127:0]
Input
IO_DDRMASTERS_0_CLK
Read data.
IO_DDRMASTERS_0_R_PAYLOAD_ID[3:0]
Input
IO_DDRMASTERS_0_CLK
Read ID tag. This signal is the identification tag for
the read data group of signals generated by the slave.
IO_DDRMASTERS_0_R_PAYLOAD_LAST
Input
IO_DDRMASTERS_0_CLK
Read last. This signal indicates the last transfer in
a read burst.
IO_DDRMASTERS_0_R_PAYLOAD_RESP[1:0]
Input
IO_DDRMASTERS_0_CLK
Read response. This signal indicates the status of the
read transfer.
IO_DDRMASTERS_0_R_READY
Output
IO_DDRMASTERS_0_CLK
Read ready. This signal indicates that the master can
accept the read data and response information.
IO_DDRMASTERS_0_R_VALID
Input
IO_DDRMASTERS_0_CLK
Read valid. This signal indicates that the channel is
signaling the required read data.
Table 12. AXI Master Write Data Channel
Port
Direction
Clock Domain
Description
IO_DDRMASTERS_0_W_VALID
Output
IO_DDRMASTERS_0_CLK
Write valid. This signal indicates that valid write
data and strobes are available.
IO_DDRMASTERS_0_W_READY
Input
IO_DDRMASTERS_0_CLK
Write ready. This signal indicates that the slave can
accept the write data.
IO_DDRMASTERS_0_W_PAYLOAD_DATA[127:0]
Output
IO_DDRMASTERS_0_CLK
Write data.
IO_DDRMASTERS_0_W_PAYLOAD_LAST
Output
IO_DDRMASTERS_0_CLK
Write last. This signal indicates the last transfer in
a write burst.
IO_DDRMASTERS_0_W_PAYLOAD_STRB[15:0]
Output
IO_DDRMASTERS_0_CLK
Write strobes. This signal indicates which byte lanes
hold valid data. There is one write strobe bit for each eight bits
of the write data bus.
JTAG Signals
The hardened RISC-V block includes two sets of JTAG signals. The soft JTAG connects
to I/O blocks while the hard JTAG connects to the JTAG User TAP interface block.
Table 13. Soft JTAG Ports
Port
Direction
Clock Domain
IO_JTAG_TCK
Input
IO_JTAG_TCK
JTAG test clock pin.
IO_JTAG_TDI
Input
IO_JTAG_TCK
JTAG test data in pin.
IO_JTAG_TDO
Output
IO_JTAG_TCK
JTAG test data out pin.
IO_JTAG_TMS
Input
IO_JTAG_TCK
JTAG mode select pin.
Table 14. Hard JTAG Ports
Port
Direction
Clock Domain
Description
JTAGCTRL_CAPTURE
Input
JTAGCTRL_TCK
Capture pin.
JTAGCTRL_ENABLE
Input
JTAGCTRL_TCK
Enable the JTAG user TAP interface.
JTAGCTRL_RESET
Input
JTAGCTRL_TCK
Reset.
JTAGCTRL_SHIFT
Input
JTAGCTRL_TCK
Shift pin.
JTAGCTRL_TCK
Input
JTAGCTRL_TCK
JTAG test clock pin.
JTAGCTRL_TDI
Input
JTAGCTRL_TCK
JTAG test data in pin.
JTAGCTRL_TDO
Output
JTAGCTRL_TCK
JTAG test data out pin.
JTAGCTRL_UPDATE
Input
JTAGCTRL_TCK
Update pin.
Custom Instruction Signals
The hardened RISC-V interface has two 32-bit custom instruction interfaces for each
CPU. The custom instructions use a type R opcode.
Table 15. Custom InstructionsWhere n is 0, 1, 2, or 3 for the CPU number.
Port
Direction
Clock Domain
Description
IO_CFUCLK
Input
Clock.
IO_CFURESET
Output
IO_CFUCLK
Reset.
CPUn_CUSTOMINSTRUCTION_CMD_READY
Input
IO_CFUCLK
Indicates that the custom processing logic is ready to process
register rs1 and rs2 from the CPU.
CPUn_CUSTOMINSTRUCTION_CMD_VALID
Output
IO_CFUCLK
Indicates that registers rs1 and rs2 are present and ready for
processing.
CPUn_CUSTOMINSTRUCTION_FUNCTION_ID[9:0]
Output
IO_CFUCLK
Function id for the custom instruction.
CPUn_CUSTOMINSTRUCTION_INPUTS_0[31:0]
Output
IO_CFUCLK
Register rs1 for the custom instruction.
CPUn_CUSTOMINSTRUCTION_INPUTS_1[31:0]
Output
IO_CFUCLK
Register rs2 for the custom instruction.
CPUn_CUSTOMINSTRUCTION_OUTPUTS_0[31:0]
Input
IO_CFUCLK
Result of the custom instruction.
CPUn_CUSTOMINSTRUCTION_RSP_READY
Output
IO_CFUCLK
Indicates that the CPU is ready to accept the custom instruction
result.
CPUn_CUSTOMINSTRUCTION_RSP_VALID
Output
IO_CFUCLK
Indicates that the custom instruction result is available.
User Interrupt Signals
Table 16. User InterruptsWhere n is a letter A-X.
Port
Direction
Description
USERINTERRUPTn
Input
Interrupt signal for a peripheral.
Clock Signals
Table 17. Clock
Port
Direction
Description
IO_PERIPHERALCLK
Input
Provides a clock for the peripherals and AXI slave
interface.
Reset Signals
Table 18. Reset
Port
Direction
Description
IO_ASYNCRESET
Input
Active-high asynchronous reset for the entire
system.
IO_SYSTEMRESET
Output
Synchronous active-high reset for the system clock.
IO_PERIPHERALRESET
Output
Synchronous active-high reset for the
peripheral clock (io_peripheralClock).
