Design Check: MIPI Lane Messages

When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error and warning messages you may encounter and explains how to fix them.

mipi_ln_rule_resource (error)

Message Resource name is empty
Resource <name> is not a valid MIPI LANE <Rx/Tx> device instance
To fix Choose a valid resource.

mipi_ln_rule_resource_excluded (error)

Message Resource <resource> is excluded in Package Planner. Please use another resource
To fix The pins for the affected resource have been excluded in the Package Planner, and cannot be assigned. Remove the excluded setting in the Package Planner or choose another resource.

mipi_ln_rule_group_clock (error)

Message No clock lane was configured in the MIPI LANE group <group>
No clock lane was configured in the same MIPI LANE group
To fix The minimum requirement to create a MIPI interface is one clock lane and one data lane. For RX, they must also be in the same MIPI group. Add a clock lane.

mipi_ln_rule_group_data (error)

Message Instance is not a resource associated to a MIPI LANE Rx group
Instance is not a valid MIPI LANE data lane resource
To fix In some packages there are not enough MIPI resources in a group to have both a clock and a data lane for RX interfaces. In those cases, you cannot use that pin as a MIPI lane. Choose another resource. See MIPI Groups by Package.

mipi_ln_rule_rx_clk_conn (error)

Message Connection type <type> is not supported by the resource
The resource does not support clock lane mode
To fix Not all resources support both GCLK and RCLK connection types. Use the Resource Assigner to pick a different resource that supports GCLK and RCLK.

mipi_ln_rule_rx_distance (error)

Message These HSIO GPIO must be placed at least 1 pair away from MIPI LANE <name> in order to avoid noise coupling from GPIO to MIPI LANE: <violated list>
To fix When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO pins between any GPIO and HSIO used as MIPI RX lanes in the same bank. This separation reduces noise.

mipi_ln_rule_rx_empty_pins (error)

Message Empty pin names found: <list>
To fix Specify the missing pin names in the list.

mipi_ln_rule_rx_param (error)

Message Invalid parameters configuration: <features>
To fix One of the parameters you set was incorrect. Review any other errors for details.

mipi_ln_rule_tx_clock (error)

Message Serial and parallel clocks cannot be the same clock
To fix You cannot use the same clock for both the serial (FASTCLK_C or FASTCLK_D) and parallel (SLOWCLK) clocks.
Message Serial clock name is not a PLL output clock
To fix Use a PLL output clock as the serial (FASTCLK_C or FASTCLK_D) clock.
Message Parallel clock name is not a PLL output clock
To fix Use a PLL output as the parallel (SLOWCLK) clock.
Message Serial and parallel clocks are not from the same PLL instance
To fix You need to use the same PLL to generate both clocks.
Message Expected clocks phase shift in <data/clock> mode: Serial: <int> degree, Parallel: <int> degree
To fix
You need to set the phase shift for the lane in clock or data model. This phase shift varies depending on the serial clock frequency (less than 500 MHz or otherwise). If your PLL is running at 500 or lower, then you can use the old 45/135 rule and it will be oK. for anything higher than that, you need to use the new 90/180 rule.
Message Expected clocks phase shift in <data/clock> mode: Valid Serial (S),Parallel (P) Combinations: (S:135 degree, P:0 degree) OR (S:180 degree, P:90 degree)
To fix Clock lanes with a serial frequency greater than or equal to 500 MHz must use the specified phase shift settings.
Message One of the clock frequencies is 0
To fix The output clock frequency is invalid. FASTCLK_D and FASTCLK_C should be the same frequency as the PHY. SLOWCLK should be 1/8 the PHY frequency. For example, if the PHY is running at 800 MHz, FASTCLK_D and FASTCLK_C should be 800 MHz and SLOWCLK should be 100 MHz.
Message Serial clock frequency has to be <n> times faster than parallel clock
To fix FASTCLK_D and FASTCLK_C should be the same frequency as the PHY. SLOWCLK should be 1/8 the PHY frequency. For example, if the PHY is running at 800 MHz, FASTCLK_D and FASTCLK_C should be 800 MHz and SLOWCLK should be 100 MHz.

mipi_ln_rule_tx_clock_region (error)

Message Serial and Parallel clocks generated by PLL have to be driven to the same clock network. <Serial | Parallel> clock <name> was generated by PLL output clock 4 that connects to regional clock network
To fix In Tz50 FPGAs, the PLL's output clock 4 can only drive the regional clock network. You should use the other clock outputs for the serial and parallel clocks.

lvds_rule_tx_distance (error)

Message These HSIO GPIO must be placed at least 1 pair away from MIPI LANE <name> in order to avoid noise coupling from GPIO to MIPI LANE: <violated list>
To fix When using HSIO pins as GPIO, make sure to leave at least 1 pair of unassigned HSIO pins between any GPIO and HSIO used as MIPI TX lanes in the same bank. This separation reduces noise.

mipi_ln_rule_tx_empty_pins (error)

Message Empty pin names found: <list>
To fix Specify the missing pin names in the list.

mipi_ln_rule_tx_param (error)

Message Invalid parameters configuration: <features>
To fix One of the parameters you set was incorrect. Review any other errors for details.

mipi_ln_rule_usage (error)

Message Resource <res name> was assigned multiple times
To fix You get this error if you choose the same resource for more than one block type (LVDS, MIPI DPHY, or GPIO).