Efinix, Inc.
  • Get Oriented
    • Interface Blocks
    • Package/Interface Support Matrix
    • Interface Block Connectivity
    • Clocking Interface Blocks
    • Designing an Interface
    • Create or Delete a Block
    • Using the Resource Assigner
      • Resource View
      • Importing and Exporting Assignments
        • Interface Scripting File
        • .csv File for GPIO Blocks
    • Editing and Viewing the Package Pinout
      • Selecting a Pin
      • Browsing for Pins
      • Drag-and-Drop Assignments
      • Excluding Pins and Banks
    • Interface Designer Output Files
    • Scripting an Interface Design
  • Device Settings
    • Configuration Interface
      • Enable Internal Reconfiguration
      • About SEU Detection
      • Enable SEU Detection
      • SEU Detection Circuitry
      • Design Check: SEU Messages
    • Design Check: Configuration Messages
    • I/O Banks Interface
    • Topaz I/O Banks
    • Dynamic Voltage Support
    • Design Check: I/O Bank Messages
  • Clock and Control Networks
    • Clock Sources that Drive the Global and Regional Networks
    • Configuring the Dynamic Clock Multiplexers
    • Driving both the Global and Regional Networks
    • Design Check: Clock Control Messages
  • DDR Interface
    • About the DDR DRAM Interface
    • Using the DDR Interface
    • Design Check: DDR Messages
  • GPIO Interface
    • Types of GPIO
    • Features for HVIO and HSIO Configured as GPIO
      • Double-Data I/O
      • Programmable Delay Chains
    • About the HVIO Interface
    • About the HSIO Interface
    • HSIO Configured as GPIO
    • Using the GPIO Block
    • Using the GPIO Bus Block
    • Create a TX Serializer Interface
    • Create a RX Deserializer Interface
    • Design Check: GPIO Messages
  • LVDS Interface
    • HSIO Configured as LVDS
    • Using the LVDS Block
    • Create an LVDS TX Interface with GCLK or RCLK
    • Create an LVDS RX Interface with GCLK or RCLK
    • Design Check: LVDS Messages
  • JTAG User TAP Interface
    • JTAG Mode
    • Using the JTAG User TAP Block
    • Design Check: JTAG User Tap Messages
  • MIPI RX/TX Lane Interface
    • HSIO Configured as MIPI Lane
    • MIPI Groups by Package
    • Using the MIPI TX Lane or MIPI RX Lane Block
    • Create a MIPI TX Interface with GCLK or RCLK
    • Create a MIPI RX Interface with GCLK or RCK
    • Design Check: MIPI Lane Messages
  • MIPI D-PHY Interface
    • MIPI RX D-PHY
    • MIPI TX D-PHY
    • Using the MIPI DPHY RX Interface
    • Using the MIPI DPHY TX Interface
    • Design Check: MIPI DPHY Messages
  • PLL Interface
    • About the PLL Interface
      • Using the PLL Block
      • Using the PLL Clock Calculator
      • Manually Configuring the PLL
      • Implementing a Zero-Delay Buffer
      • Design Check: PLL Messages
    • About the Fractional PLL Interface
      • Using the Fractional PLL Block
      • Using the Fractional PLL Clock Calculator
      • Design Check: Fractional PLL Messages
    • Understanding PLL Phase Shifting
    • About the Spread-Spectrum Clocking PLL Interface
      • Using the SSC PLL Block
      • Design Check: PLL SSC Errors
  • Oscillator
    • Using the Oscillator Block
    • Design Check: Oscillator Messages
  • Hardened RISC-V Block Interface
    • Using the Hardened RISC-V Block
    • Design Check: RISC-V Messages
  • Ethernet SGMII Interface
    • Ethernet SGMII Base Tab
    • Ethernet SGMII Control Register Tab
    • Ethernet SGMII Pins Tab
    • Ethernet SGMII Common Properties Tab
    • Using the Ethernet SGMII Interface
    • Design Check: Ethernet SGMII Messages
  • Ethernet XGMII Interface
    • Ethernet XGMII Base Tab
    • Ethernet XGMII Control Register Tab
    • Ethernet XGMII Pins Tab
    • Ethernet XGMII Common Properties Tab
    • Using the Ethernet XGMII Interface
    • Design Check: Ethernet XGMII Messages
  • PMA Direct Interface
    • PMA Direct Base Tab
    • PMA Direct Control Register Tab
    • PMA Direct Pins Tab
    • PMA Direct Common Properties Tab
    • PMA Direct Bonding Mode
    • Design Check: PMA Direct Messages
  • Transceiver Interfaces (Common Settings)
    • Transceiver PLLs
    • Quad-Lane Settings
  • PCI Express Interface
    • PCI Express Base Tab
    • PCI Express Reset Tab
    • PCI Express Function Tab
    • PCI Express RP Outbound Tab
    • PCI Express Device Capability Tab
    • PCI Express Slot Capabilities Tab
    • PCI Express Pins Tab
    • Using the PCI Express Interface
      • GPIO Block (PERST_N)
      • Reference Clock
      • Oscillator
      • Enable Configuration User Status Pin
    • Design Check: PCI Express Messages
  • Interface Floorplans

JTAG User TAP Interface

Topaz™ FPGAs have dedicated JTAG pins to for configuration and boundary scan testing.

  • JTAG Mode
  • Using the JTAG User TAP Block
  • Design Check: JTAG User Tap Messages

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