Using the Hardened RISC-V Block

To use the Topaz hardened RISC-V block you add it to your interface design and configure the settings.

Instead of manually adding a RISC-V block to your interface design, Efinix recommends that you use the IP Manager to create a Sapphire High-Performance SoC instance. The IP Manager automatically creates all the Interface Designer blocks that you need for the SoC, so you do not have to add them manually.

Important: If you use the IP Manager to generate the Interface Designer blocks, do not change the settings of those blocks later in the Interface Designer. Otherwise, you will break your design.

Exception: You can specify a configuration file for on-chip RAM in the Quad-Core RISC-V > Block Editor > Base tab.

Table 1. Base Tab
Parameter	Choices	Description
Instance Name	User defined	Enter the instance name.
SOC Resource	SOC_0	Choose the resource. The IP Manager chooses SOC_0 by default.
On-Chip Ram Configuration File	User specified	Indicate the file for the on-chip memory configuration. You can specify the filename even if you auto-generated the RISC-V block with the IP Manager.

Table 2. Clock/Control Tab
Parameter	Choices	Description
System Clock Source	None, Clock 0, Clock 1, Clock 2	Choose the clock source. The IP Manager chooses the resource PLL_BL0 and Clock 0 for the system clock.
Memory Clock Source	None, Clock 0, Clock 1, Clock 2	Choose the clock source. The IP Manager chooses the resource PLL_BL1 and Clock 1 for the memory clock.
Active-High Periphery Controller Reset Pin Name	User defined	Efinix recommends you use the default pin names.
Active-High System Reset Pin Name
Active-High asynchronous reset for SOC Pin Name
Periphery Controller Clock Pin Name
Invert Periphery Controller Clock Pin	On, off (default)	Turn on to invert the clock.

Table 3. User AXI Master Tab
Parameter	Choices	Description
Enable AXI Master Interface	On, off	Turn on to enable the interface. If you turn on the AXI Master in the IP Manager, the IP Manager enables the interface.
User AXI Master Clock Pin Name	User defined	Enter the pin name. If you turn on the AXI Master in the IP Manager, the IP Manager enters the default pin name.
Invert User AXI Master Clock Pin	On, off	Turn on to invert the clock.
User AXI Master Reset Pin Name	User defined	Enter the pin name. If you turn on the AXI Master in the IP Manager, the IP Manager enters the default pin name.
Read Address Channel tab Write Address Channel tab Write Response Channel tab Read Data Channel tab Write Data Channel tab	User defined	The Interface Designer shows default names for the AXI pins. Efinix recommends you keep the default values.

Table 4. User AXI Slave Tab
Parameter	Choices	Description
User AXI Slave Channel Interrupt Pin Name	User defined	Enter the pin name. The IP Manager enters the default pin name.
Read Address Channel tab Write Address Channel tab Write Response Channel tab Read Data Channel tab Write Data Channel tab	User defined	The Interface Designer shows default names for the AXI pins. Efinix recommends you keep the default values.

Table 5. Custom Instruction TabWhere n is the interface number (0, 1, 2, or 3)
Parameter	Choices	Description
Eable Custom Instruction Interface n	On, off	Turn on to enable the interface.
Active Synchronous Reset for Custom Instruction Unit Pin Name	User defined	Enter the pin name.
Custom Instruction Unit Clock Pin Name	User defined	Enter the pin name.
Invert Custom Instruction Unit Clock Pin Name	On, off	Turn on to invert the pin.
Interface n tab	User defined	The Interface Designer shows default names for the custom instruction pins. Efinix recommends you keep the default values.

Table 6. External Interrupt TabWhere x is a letter (A-X)
Parameter	Choices	Description
External Interrupt x: Pin Name	User defined	Enter the pin name.

Table 7. Debug Tab
Parameter	Choices	Description
JTAG Interface Type	FPGA, CPU, DISABLE	DISABLE: Do not use the JTAG interface. FPGA: Connect the interface to the JTAG User Tap. CPU: Connect the interface to GPIO pins.
Pin Names	User defined	Enter the pin names.