Interface Floorplans

Note: The numbers in the floorplan figures indicate the HVIO and HSIO number ranges. Some packages may not have all HVIO or HSIO pins in the range bonded out. Refer to the pinout for information on which pins are available in each package.

Floorplan Diagram for FPGAs in F100 Packages

Figure 1. Tz50 FPGAs

Floorplan Diagram for FPGAs in F225 and F256 Packages

Figure 2. Tz50 FPGAs

Floorplan Diagram for FPGAs in J361 Packages

Figure 3. Tz110 and Tz170 FPGAs

Floorplan Diagram for FPGAs in G400 Packages

Figure 4. Tz110 and Tz170 FPGAs

Floorplan Diagram for FPGAs in N441 Packages

Figure 5. Tz75 and Tz100 FPGAs

Floorplan Diagram for FPGAs in J484 Packages

Figure 6. Tz110 and Tz170 FPGAs

Floorplan Diagram for FPGAs in N484 Packages

Figure 7. Tz200 and Tz325FPGAs

Figure 8. Tz75 and Tz100 FPGAs

Floorplan Diagram for FPGAs in C529 Packages

Figure 9. Tz200 and Tz325 FPGAs

Floorplan Diagram for FPGAs in N576 Packages

Figure 10. Tz75 and Tz100 FPGAs

Floorplan Diagram for FPGAs in N676 Packages

Figure 11. Tz75 and Tz100 FPGAs

Floorplan Diagram for FPGAs in N900 Packages

Figure 12. Tz200 and Tz325FPGAs