Design Check: GPIO Messages
When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error and warning messages you may encounter and explains how to fix them.
bus_rule_members_consistent (error)
| Message | Bus <name> has mismatch properties with its members Members of
bus <name> has inconsistent shared pin/register settings with
<member>: <inconsistent_members_name> |
| To fix | The properties you have set for the bus are inconsistent with the settings for the bus members. Review the settings and fix any mismatches. |
bus_rule_name (error)
| Message | Bus name is empty Valid characters are alphanumeric characters with
dash and underscore only |
| To fix | Specify a valid bus name. |
gpio_rule_inst_name (error)
| Message | Instance name is empty |
| To fix | Specify a valid bus name. |
| Message | GPIO name <instance name> is used |
| To fix | The GPIO name <instance name> is already in use. Specify a different instance name. |
gpio_rule_input_mode (error)
| Message | For input mode, input must be configured |
| To fix | You need to configure the input parameters. |
| Message | For input mode, input pin name must be configured |
| To fix | Specify a name for the input pin. |
| Message | Input pin name with square bracket does not match a bus name with index |
| To fix | You probably used a bracket [ or ] in the pin name. Rename the pin without brackets. |
gpio_rule_input_register (error)
| Message | Input clock pin name is empty Input clock pin name has illegal
character |
| To fix | If you are using the register option, you need to specify a valid clock pin name. |
gpio_rule_input_register (warning)
| Message | Input clock pin name is empty Input clock pin name has illegal
character |
| To fix | If you have a GPIO block in inout mode, you get this message if you do not specify an input pin name or if you use invalid characgters in the name. You should specify a name to use the pin as bidirectional. |
| Message | Alternate input connection cannot be registered |
| To fix | When you are using an alternate connection type. you cannot use the register. Set Register Option to none. |
gpio_rule_output_mode (error)
| Message | For output mode, output must be configured |
| To fix | You need to configure the output parameters. |
| Message | For output mode without constant output, output pin name must be configured |
| To fix | For GPIO output blocks, you can drive them as 0 or a 1 with the Constant Output option. In that mode, you do not need to specify an output pin name. If you are using Constant Output set to none (as you would for a regular output pin), you need to specify a pin name. |
| Message | Output pin name with square bracket does not match a bus name with index |
| To fix | You probably used a bracket [ or ] in the pin name. Rename the pin without brackets. |
gpio_rule_inout_mode (error)
| Message | For inout mode, both output and output enable must be configured |
| To fix | When using a GPIO block in inout mode, you need to set the options for the output and output enable (as well as the input). |
| Message | For inout mode, both output pin name and output enable pin name must be configured |
| To fix | Specify a valid name for the output pin and output enable pin. |
| Message | Output enable pin name with square bracket does not match a bus name with index |
| To fix | You probably used a bracket [ or ] in the pin name. Rename the pin without brackets. |
gpio_rule_clkout_mode (error)
| Message | For clkout mode, output must be configured |
| To fix | When using a GPIO block in clkout mode, you need to set all of the options. |
| Message | For clkout mode, output clock pin name must be configured |
| To fix | When using a GPIO block in clkout mode, you need to specify a valid pin name for the ouput clock. |
gpio_rule_output_clock (error)
| Message | Output is registered but clock pin name is empty |
| To fix | If you choose register or inv_register as the Register Option, then you also need to specify an output clock pin name. |
| Message | Output enable is registered but clock pin name is empty |
| To fix | If you are using a GPIO in inout mode, you need to specify the output enable pin name if you set the output enable to register. |
| Message | Output is registered but clock pin name has illegal
character Output enable is registered but clock pin name has illegal
character |
| To fix | Use valid names for these pins. |
| Message | Output clock pin name is not the same as output enable clock pin name |
| To fix | For a GPIO block in inout mode, you need to use the same pin names for the output clock pin and the output enable clock pin. |
| Message | Output clock inversion is not the same as output enable clock inversion |
| To fix | For a GPIO block in inout mode, if you invert the output clock pin you also need to invert the output enable clock pin. Similarly, if you do not invert the output clock pin, you cannot invert the output enable clock pin. |
gpio_rule_unused_mode (error)
| Message | For unused (none) mode, its state needs to be configured |
| To fix | If you set a GPIO block mode to none, you need to set the Unused State. The default is input with weak pull-up. You can change this setting globally by clicking the GPIO category in the Design Explorer and setting the Unused State option. |
gpio_rule_input_alt_conn (error)
| Message | Connection type <type> is not supported by <resource> |
| To fix | If you want to use the alternate funciton of a GPIO block, you need to choose a resource that supports it. For example, global clock (GCLK) is only supported on the P pin. You can filter for resources by alternate function in the Resource Assigner. |
| Message | <resource> only supports normal connection type |
| To fix | You need to choose a different connection type or assign a different resource that supports the connection type you want to use. You can filter for resources by alternate function in the Resource Assigner. |
gpio_rule_input_alt_conn (warning)
| Message | Connection type <type> is not supported by <resource> |
| To fix | For a GPIO block in inout mode, you get a warning if you do not specify the input pin name. Specify the input pin name to use the block as bidirectional or leave it empty to use it as open-drain. |
| Message | <resource> only supports normal connection type |
| To fix | The software thinks you are creating an open-drain if you leave the input pin name empty, so this choice is valid, but it lets you know that you made this selection in case you really want to use it as bidirectional. |
gpio_rule_ddio_resource (error)
| Message | Double Data I/O must be assigned to resource that supports DDIO |
| To fix | To use the DDIO feature, you need to pick a resource that supports it. You can filter for resources by DDIO in the Resource Assigner Features column. |
gpio_rule_ddio_resource (warning)
| Message | Double Data I/O must be assigned to resource that supports DDIO |
| To fix | You get this error if you use a resource that does not support DDIO but have not yet specified an input pin name. Either turn off DDIO or choose a resource that supports it. You can filter for resources by DDIO in the Resource Assigner Features column. |
gpio_rule_ddio_input (error)
| Message | Input with DDIO requires register option to be set |
| To fix | If you are using DDIO, you must set the the Register Option to register. |
gpio_rule_ddio_input (warning)
| Message | Input with DDIO requires register option to be set |
| To fix | For a GPIO block in inout mode, if the Double-Data I/O Option is other than none, you need to choose register as the Register Option. You get this warning when you have set some options for the input pin but have not yet specified a pin name. |
gpio_rule_ddio_output (error)
| Message | Output with DDIO requires register option to be set |
| To fix | To use DDIO you must set the Double-Data I/O Option set to something other than none. |
gpio_rule_ddio_pin_name (error)
| Message | Double Data I/O must have both HI and LO input pin names defined |
| To fix | When using DDIO, you need to specify pin names for the Pin Name (HI) and Pin Name (LO). |
gpio_rule_ddio_pin_name (warning)
| Message | Double Data I/O must have both HI and LO input pin names defined |
| To fix | For a GPIO block in inout mode, if the Double-Data I/O Option is other than none, you need to specify pin names for the Pin Name (HI) and Pin Name (LO). You get this warning when you have set some options for the input pin but have not yet specified these pin names. |
gpio_rule_alt_conn (warning)
| Message | Connection type <type> must be used by valid PLL |
| To fix | The GPIO is connected to a PLL clock input but is the resource you assigned does not support the pll_clkin alternate function. Choose a different resource that supports it. You can filter resources by alternate function in the Resource Assigner. |
| Message | Connection type <type> cannot be used on an unbonded resource |
| To fix | You get this error if the resource you choose is not available in the FPGA/package combination you are using. Choose another resource. |
| Message | pll_clkin connection to PLL clock source not being used in <instance> |
| To fix | The GPIO block is set to be a PLL reference clock (pll_clkin connection type) but the PLL is not configured to use it. Make sure that the clock you are choosing in the PLL is associated with this GPIO's resource. |
| Message | pll_clkin connection to PLL clock source but none of the external clock source in PLL <instance> is selected |
| To fix | The GPIO block is set to be a PLL reference clock (pll_clkin connection type) but the PLL is not configured to use it. In the PLL block, choose external or dynamic as the Clock Source and make sure that the clock you are choosing is associated with this GPIO's resource. |
| Message | pll_clkin connection to PLL clock source but PLL Clock source on <instance> is set to core |
| To fix | The GPIO block is set to be a PLL reference clock (pll_clkin connection type) but the PLL is not configured to use it. In the PLL block, choose external or dynamic as the Clock Source and make sure that the clock you are choosing is associated with this GPIO's resource. |
| Message | pll_extfb connection to PLL external feedback pin on <instance> is not set to external |
| To fix | The GPIO block is set to be external feedback for the PLL (pll_extfb connection type) but the PLL is not configured to use it. In the PLL Clock Calculator, choose External as the Feedback Mode. |
gpio_rule_sample_device (error)
| Message | Unsupported features in ES device: <features> |
| To fix | You get this error when you try to use a feature that is not supported in an engineering sample (ES) version of the FPGA. |
gpio_rule_resource (error)
| Message | Resource name is empty Resource is not a valid GPIO device
instance |
| To fix | You need to choose a valid resource. |
gpio_rule_resource_excluded (error)
| Message | Resource <resource> is excluded in Package Planner. Please use another resource |
| To fix | The pins for the affected resource have been excluded in the Package Planner, and cannot be assigned. Remove the excluded setting in the Package Planner or choose another resource. |
gpio_rule_io_standard_bank (warning)
| Message | Mismatch voltage in I/O standard assignment in bank (<voltage>) and instance (<io_std>) |
| To fix | You get this error when the voltage for the I/O bank does not match the I/O standard you chose for the GPIO. Either change the I/O bank voltage or choose a compatible I/O standard. |
gpio_rule_io_standard_compatibility (error)
| Message | I/O standard <value> is not supported in bank <bank> |
| To fix | You get this error when you choose an I/O standard that is not
supported in the bank. You need to choose another I/O standard or pick a
resource in another bank. See Topaz I/O Banks for
the voltages supported in each bank.
See Types of GPIO for the I/O standards the GPIO support.
|
gpio_rule_drive_strength (error)
| Message | Valid drive strength for <iostd> is: <list> |
| To fix | Choose the drive strength based on the recommendation in the message. |
| Message | Invalid drive strength <value> for <iostd>. Check for valid I/O standard |
| To fix | Confirm the drive strengths that are allowed for the I/O standard you want to use and then change the setting accordingly. |
gpio_rule_ddio_serial (error)
| Message | DDIO has to be none when serialization is enabled on both input and
output DDIO on input has to be none when deserialization is
enabled DDIO on output has to be none when serialization is
enabled |
| To fix | You cannot use DDIO and serialization or deserialization at the same time. Turn one of them off. |
gpio_rule_transmit_toggling (warning)
| Message | Bank <name> has <int> GPIO in inout/output mode that exceed max limit of <int> which can result in LVTTL simultaneous switching noise |
| To fix | If you use more than 6 HVIO pins as GPIO in output or inout mode in the same bank, it can cause switching noise. Instead, use resources from another bank. |
gpio_rule_serial_input_clk (error)
| Message | Input clock inversion is not allowed with deserialization enabled |
| To fix | If you use deserialization, you cannot also invert the clock. Turn off the Inverted option. |
gpio_rule_serial_output_clk (error)
| Message | Output clock inversion is not allowed with serialization enabled |
| To fix | If you use serialization, you cannot also invert the clock. Turn off the Inverted option. |
gpio_rule_static_input_delay (error)
| Message | Static delay, <int> is outside of limit (0-15) for non-Differential
HSTL/SSTL I/O Standard Static delay, <int> is outside of limit (0-63)
for Differential HSTL/SSTL I/O Standard |
| To fix | The static input delay you selected is not valid. Use a number in the range specified in the message. |
gpio_rule_io_standard_valid (error)
| Message | I/O standard <value> is not supported in bank <bank> |
| To fix | You get this error when you choose an I/O standard that is not
supported in the bank. You need to choose another I/O standard or pick a
resource in another bank.
See Topaz I/O Banks for the voltages supported in each bank
|
gpio_rule_hsio_usage (error)
| Message | HSIO resource <name> was assigned to GPIO, LVDS and MIPI
LANE HSIO resource <name> was assigned to both GPIO and
LVDS HSIO resource <name> was assigned to both GPIO and
MIPI LANE |
| To fix | You get this error if you try to use the same resource for more than one block type. Remove blocks so that you only are only using the resource once. |
gpio_rule_io_standard_stl (error)
| Message | This resource is reserved as vref for bank <name>. Use a different resource to configure single ended HSTL/SSTL |
| To fix | Some resources can be used as the VREF for an I/O standard. If you are using an I/O standard that uses a VREF pin, you must use this resource as a VREF. Choose another resource for the GPIO function. |
| Message | GPIO <name> has to be configured as vref input mode to support I/O
standard <iostd> GPIO <name> has to be configured as vref input
connection type to support I/O standard <iostd> GPIO
<name> has to be configured as vref input to support I/O standard
<iostd> |
| To fix | If you are using an I/O standard that uses a VREF pin, you must use this resource as a VREF. Configure the GPIO as an input and choose vref as the Connection Type. |
| Message | I/O Standard <iostd> cannot be used due to unbonded vref resource on
the same bank <name> I/O Standard <iostd> cannot be used due to
vref resource not bonded out |
| To fix | If a VREF pin is not available in the I/O bank (e.g., it is not in the FPGA/package you chose), you cannot use an I/O standard that requires it. Instead choose a different I/O standard for the GPIO or a resource in a different I/O bank that has a VREF pin bonded out. . |
gpio_rule_io_standard_stl (warning)
| Message | Skip checking Vref requirement on a single-ended input configuration: input path is not used |
| To fix | You get this warning when the GPIO is in inout mode but you have not specified an input pin name. |
gpio_rule_io_standard_differential (error)
| Message | GPIO resource, <name> with differential I/O standard was configured
for multiple use Differential I/O standard can only be assigned to pad P
resource |
| To fix | You cannot use differential HSTL/SSTL for the N resource. Change the resource to a P one. |
| Message | Differential I/O standard is not valid on GPIO resource <name> due to the corresponding N resource not bonded |
| To fix | To use a differential I/O standard, both the N and P resources must be available. If the N resource is not bonded out, then you cannot use a differential standard. Choose another pair of N and P resources. |
gpio_rule_dynamic_delay (error)
| Message | Input dynamic delay is not supported in non-P resource, <resname> |
| To fix | The HSIO N resource does not support dynamic delay. Either change the delay to static or pick a P resource. |
| Message | Clock pin name in input dynamic delay is empty |
| To fix | When using the dynamic delay, you need to specify a clock input pin name. |
gpio_rule_serialization (error)
| Message | Register Option has to be set to register when using serialization |
| To fix | You cannot use serialization unless the Register Option is set to register. Either change the option or do not use serialization. |
| Message | Serialization cannot be used with DDIO Option |
| To fix | If you are using serialization, you cannot also use DDIO. Either disable serialization or set Double Data I/O Option to none. |
| Message | Serial and parallel clock names are required to be non-empty with serialization |
| To fix | You need to specify the parallel and serial clock names if you are using serialization. |
| Message | Serialization is not supported due to PLL is not available |
| To fix | When the GPIO is using the serializer, the serial and parallel clock signals must come from a PLL. You need to make two PLL clock outputs available to the GPIO. |
| Message | Serial and parallel clocks cannot be the same clock |
| To fix | Use different PLL output clocks for the signals. |
| Message | Serial and parallel clock names are not PLL output clocks Serial
clock name is not a PLL output clock Parallel clock name is
not a PLL output clock |
| To fix | When the GPIO is using the serializer, the serial and parallel clock signals must come from a PLL. You need to use two PLL clock outputs, one for serial and one for parallel. |
| Message | Serial and parallel clocks are not from the same PLL instance |
| To fix | Use PLL output clocks from the same PLL for the serial and parallel clocks. |
| Message | One of the clock frequencies is 0 |
| To fix | Change the clock frequency to be something other than zero. |
| Message | Serial clock frequency has to be 4 times faster than parallel clock |
| To fix | Change the PLL output clock frequencies such that the serial clock is 4 times faster than the parallel clock. |
| Message | Invalid phase shift difference: <phase shift difference> = Serial: <serial clk shifted time> - Parallel: <parallel clk shifted time> (max=<max shift difference allowed>, min=<min shift difference allowed>) |
| To fix | Adjust the phase shift for the serial clock and parallel clock to ensure that the phase-shifted time difference falls within the range of 45 to 135 degrees, relative to the phase-shifted time of the serial clock. |
gpio_rule_deserialization (error)
| Message | Register Option has to be enabled when using deserialization |
| To fix | You cannot use deserialization unless the Register Option is set to register. Either change the option or do not use deserialization. |
| Message | Deserialization canot be used with DDIO Option |
| To fix | If you are using serialization, you cannot also use DDIO. Either disable deserialization or set Double Data I/O Option to none. |
| Message | Serial and parallel clock names are required to be non-empty with deserialization |
| To fix | You need to specify the parallel and serial clock names if you are using deserialization. |
| Message | Deserialization is not supported due to PLL is not available |
| To fix | When the GPIO is using the deserializer, the serial and parallel clock signals must come from a PLL. You need to make two PLL clock outputs available to the GPIO. |
| Message | Serial and parallel clocks cannot be the same clock |
| To fix | Use different PLL output clocks for the signals. |
| Message | Serial and parallel clock names are not PLL output clocks Serial
clock name is not a PLL output clock Parallel clock name is
not a PLL output clock |
| To fix | When the GPIO is using the deserializer, the serial and parallel clock signals must come from a PLL. You need to use two PLL clock outputs, one for serial and one for parallel. |
| Message | Serial and parallel clocks are not from the same PLL instance |
| To fix | Use PLL output clocks from the same PLL for the serial and parallel clocks. |
| Message | One of the clock frequencies is 0 |
| To fix | Change the clock frequency to be something other than zero. |
| Message | Serial clock frequency has to be 4 times faster than parallel clock |
| To fix | Change the PLL output clock frequencies such that the serial clock is 4 times faster than the parallel clock. |
| Message | Invalid phase shift difference: <phase shift difference> = Serial: <serial clk shifted time> - Parallel: <parallel clk shifted time> (max=<max shift difference allowed>, min=<min shift difference allowed>) |
| To fix | Adjust the phase shift for the serial clock and parallel clock to ensure that the phase-shifted time difference falls within the range of 45 to 135 degrees, relative to the phase-shifted time of the serial clock. |
gpio_rule_bus_hold (error)
| Message | Bus hold is only supported on 1.2/1.5/1.8 V LVCMOS I/O standard HSIO only |
| To fix | You cannot use the bus hold option for the I/O standard you chose. Either turn off Enable Bus Hold or use a different I/O standard. |
gpio_rule_differential_stl_inout (error)
| Message | For inout mode with differential STL, output enable (N) pin name must be configured |
| To fix | Specify the output enable pin name. |
gpio_rule_cfg_io_standard_valid (error)
| Message | Unsupported I/O standard |
| To fix | The I/O standard you chose is not supported. Choose another one. Refer to Types of GPIO. |
gpio_rule_cfg_slew_rate (error)
| Message | Resource <name> does not support Slew Rate feature. It will be ignored |
| To fix | The Topaz HVIO pins do not support slew rate. Either diable that option or choose another resource. |
gpio_rule_cfg_dyn_delay (error)
| Message | Resource <name> does not support Dynamic Delay feature. |
| To fix | The resource you used does not support dynamic delay. Refer to Features for HVIO and HSIO Configured as GPIO for which GPIO support that feature. Either turn off dynamic delay or choose another resource that supports it. |
gpio_rule_cfg_bus_hold (warning)
| Message | Resource <name> does not support Bus Hold feature. It will be ignored |
| To fix | Not all resources support bus hold. Refer to Features for HVIO and HSIO Configured as GPIO for which GPIO support that feature. Either turn off bus hold or choose another resource that supports it. |
gpio_rule_cfg_dyn_pullup (warning)
| Message | Resource <name> does not support Dynamic Pullup feature. It will be ignored |
| To fix | Not all resources support dynamic pullup. Refer to Features for HVIO and HSIO Configured as GPIO for which GPIO support that feature. Change the Pull Option or choose another resource that supports it. |
gpio_rule_cfg_serialization (error)
| Message | Resource <name> does not support Serialization feature. |
| To fix | Not all resources support serialization. Refer to Features for HVIO and HSIO Configured as GPIO for which GPIO support that feature. Turn off serialization or choose another resource that supports it. |
gpio_rule_cfg_deserialization (error)
| Message | Resource <name> does not support Deserialization feature. |
| To fix | Not all resources support deserialization. Refer to Features for HVIO and HSIO Configured as GPIO for which GPIO support that feature. Turn off deserialization or choose another resource that supports it. |