MIPI D-PHY Interface

Important: All information is preliminary and pending definition.
Important: Tz75, Tz100, Tz200, Tz325: All information is preliminary and pending definition.

In addition to the HSIO, which you can configure as MIPI RX or TX lanes, Topaz FPGAs have hardened MIPI D-PHY blocks, each with 4 data lanes and 1 clock lane. The MIPI D-PHY RX and MIPI D-PHY TX can operate independently with dedicated I/O banks.

You can use the hardened MIPI D-PHY blocks along with the HSIO configured as MIPI D-PHY lanes to create systems that aggregate data from many cameras or sensors.

The MIPI TX/RX interface supports the MIPI D-PHY specification v1.1. It has the following features:

  • Programmable data lane configuration supporting up to 4 lanes
  • High-speed mode supports up to 2.0 Gbps data rates per lane
  • Operates in continuous and non-continuous clock modes
  • Supports Ultra-Low Power State (ULPS)