Enable Configuration User Status Pin

You may want your PCIe application to know when the link is ready for TLP transactions. Your application can monitor the FPGA’s configuration user status pin. This signal is generated by the FPGA’s configuration control block. When the FPGA asserts this status signal, your application can start TLP transactions.

Important: When you are using the PCI Express block, you must enable the configuration user status pin. Otherwise the Interface Designer issues an error. See configuration_rule_in_user_pin.

To enable this signal in the Interface Designer:

  1. Go to Device Setting > Configuration > User Status tab.
  2. Turn on Enable User Status Control. The User Status Pin Name shows cfg_USR_STATUS. This status pin can drive your PCIe application.
Notice: Refer to "Link Up" in the Titanium PCIe® Controller User Guide for a timing diagram showing the cfg_USR_STATUS signal during link up.