Clock Sources that Drive the Global and Regional Networks

The Topaz global and regional networks are highly flexible and configurable. Clock sources can come from interface blocks, such as GPIO or PLLs, or from the core fabric.

Note: For more information on the clock sources that can drive the global and regional networks, refer to the data sheet.

Table 1. Clock Sources that Drive the Global and Regional Networks
Source	Description
GPIO	Supports GCLK and RCLK. (Only the P resources support this connection type).
LVDS RX	Supports GCLK and RCLK.
MIPI RX Lane (configured as clock lane)	Supports GCLK (default) and RCLK. You can only use resources that are identified as clocks.
PLL	Tz50: Output clocks 0 - 3 connect to the global network. Output clock 4 only connects to the regional network in the top or bottom interface regions (depending on the location of the PLL) and can only drive interface blocks on the top or bottom of the FPGA. All output clocks connect to the global network. All others: All output clocks connect to the global network. Some PLLs can also drive the regional clock network; see "Driving the Regional Network" in the data sheet for details.
Oscillator	Connects to global buffer.
Core	Signals from the core logic can drive the global or regional network.

Note: Some clock sources can drive both the global and regional networks. See Driving both the Global and Regional Networks for instructions on using both.