Topaz I/O Banks

Efinix FPGAs have input/output (I/O) banks for general-purpose usage. Each I/O bank has independent power pins. The number and voltages supported vary by FPGA and package.

Some I/O banks are merged at the package level by sharing VCCIO pins, these are called merged banks. Merged banks have underscores (_) between banks in the VCCIO name (e.g., 1B_1C means VCCIO for bank 1B and 1C are connected). Some of the banks in a merged bank may not have available user I/Os in the package. The following table lists banks that have available user I/Os in a package.

Table 1. Topaz I/O Banks by Package for Tz50 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
F100 1A, 2A 1.2, 1.35, 1.5, 1.8 All 1A_4B, 2A_2B
1B, 3A, 3B 1.2, 1.35, 1.5, 1.8 All 3B_4A
BL 1.8, 2.5, 3.0, 3.3 All
F225
F256
BL, TL, TR, BR, 1.8, 2.5, 3.0, 3.3 All
1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B 1.2, 1.35, 1.5, 1.8 All
Table 2. Topaz I/O Banks by Package for Tz75 and Tz100 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
N441 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 All
BL2, BR0, BR1, TL3, TR1 1.8, 2.5, 3.0, 3.3 All
N484 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 All
BL3, TR1, BR0, BR1 1.8, 2.5, 3.0, 3.3 All BR1_BL3
N576 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 All
BL2, BL3, BR0, BR1, TL3, TR1 1.8, 2.5, 3.0, 3.3 All
N676 2A, 2B, 2C, 4A, 4B 1.2, 1.35, 1.5, 1.8 All
BL0, BL1, BL2, BL3, BR0, BR1, TL2, TL3, TR1, TR2, TR3, TR5 1.8, 2.5, 3.0, 3.3 All
Table 3. Topaz I/O Banks by Package for Tz110 and Tz170 FPGAs
Package I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
J361 2B, 2C, 3A, 3B, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 All 2A_2B, 3B_3C
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All
J484 2B, 3A, 3B, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 All 2A_2B_2C, 3B_3C
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All
G400 2A, 2B, 2C, 3A, 3B, 3C, 4A, 4B, 4C 1.2, 1.35, 1.5, 1.8 All
BL, TL, TR, BR 1.8, 2.5, 3.0, 3.3 All
Table 4. Topaz I/O Banks by Package for Tz200 and Tz325 FPGAs
Package GPIO Type I/O Banks Voltage (V) Dynamic Voltage Support DDIO Support Merged Banks
N484 HSIO 2B, 2C, 2D, 2E, 4B, 4C, 4D 1.2, 1.35, 1.5, 1.8 All 2A_2B_2C, 4A_4B
HVIO BR0, BR3, TR1 1.8. 2.5, 3.0, 3.3 Yes All BR3_BR4
C529 HSIO 2A, 2B, 2C, 2D, 2E, 4B, 4C, 4D 1.2, 1.35, 1.5, 1.8 All 4A_4B
HVIO BL2, BL3, BR0, BR3, TL1, TL5, TR0, TR1, TR2 1.8. 2.5, 3.0, 3.3 Yes All BR3_BR4,
TL1_TL5
BL2_BL3
N900 HSIO 2A, 2B, 2C, 2E, 4A, 4B, 4C, 4D 1.2, 1.35, 1.5, 1.8 All
HVIO BL2, BL3, BR0, BR3, BR4, TL0, TR1 1.8. 2.5, 3.0, 3.3 Yes All TL1_TL5
Notice: Refer to the FPGA pinout for information on the I/O bank assignments.