Revision History
| Date | Version | Description |
|---|---|---|
| January 2026 | 2.7 | Added PMA Direct messages. (DOC-2867) |
| December 2025 | 2.6 | Added PCIe root port, slot capability,
and hot plug descriptions. Corrected definition for MIPI D-PHY
signal ERR_SOT_HS_LANn; SOT is start of transmission.
(DOC-2755)The lvds_rule_rx_distance message is changed from an
error to a warning. (DOC-2833) Added more PCIe messages in
Design Check: PCI Express Messages. (DOC-2833) Corrected
instructions in Create an LVDS TX Interface with GCLK or RCLK and
Create an LVDS RX Interface with GCLK or RCLK.
(DOC-2736) |
| November 2025 | 2.5 | Added note about not mixing 3- and 4-byte address modes to Enable Internal Reconfiguration. (DOC-2704) In Design
Check topics, added message about excluded pins.
(DOC-2739) |
| September 2025 | 2.4 | Updated Figure 4; some N signals were incorrectly labeled as P. (DOC-2676) Added
FPLL_V1 in Table 1. (DOC-2679) |
| August 2025 | 2.3 | Added Rx Polarity Inversion and Tx Polarity Inversion parameters to PMA Direct Control Register Tab. (DOC-2668) |
| July 2025 | 2.2 | Added new warning message to Design Check: Configuration Messages. (DOC-2614) Removed Link Port Number from PCI Express Device Capability Tab. (DOC-2593) Added Amplitude
Boost and Edge Boost parameters to PMA Direct Control Register Tab. (DOC-2590) Added
pma_direct_custom_data_rate (error) and
pma_direct_custom_data_rate (warning) messages.
(DOC-2601) Added newly supported packages in v2025.1.110.3.x. |
| June 2025 | 2.1 | Added note that user should perform IBIS simulation to
determine which settings to use for the DDR block (VREF and DQ
settings). (DOC-2432) When enabling the HSIO dynamic delay, the
delay is updated on the rising edge of DLYCLK.
(DOC-2531) Fix typos. (DOC-2537) The HyperRAM
block has five new options to set the drive strength of the clock,
reset, chip select, data strobe, and bus signals.
(DOC-2570) Added Design Check message for HyperRAM drive
strength check. (DOC-2570) |
| May 2025 | 2.0 | Updated interface floorplan diagrams.
Updated Package/Interface Support Matrix. Added
Enable SLVS option to Table 2. Added new warning messages to Design Check: RISC-V Messages. (DOC-2252) Updated
messages for clock and control, LVDS (DOC-2453), PLL (DOC-2335),
and oscillator. Corrected choice range for PLL clock
divider. (DOC-2524)
Added transceiver interface descriptions.
Added fractional PLL interface description. |
| March 2025 | 1.3 | Updated note in Enable Internal Reconfiguration to reflect revised title of linked document. (DOC-2301) |
| January 2025 | 1.2 |
The clock_rule_lvds_rx_clock_source message is a warning not an
error. (DOC-2308)
|
| December 2024 | 1.1 | Added Tz200 and Tz325. Updated interface diagrams to align with resource naming in Efinity software. |
| November 2024 | 1.0 | Initial release for Efinity software v2024.2. |