About the SPI Flash Memory

The QFP100F3 packages include a Trion FPGA and a SPI flash memory. The SPI flash memory has a density of 16 Mbits and a clock rate of up to 20 MHz. In active configuration mode, the FPGA is configured using the configuration bitstream in the SPI flash memory. Typically you can fit two bitstream images into the QFP100F3 SPI flash.

In SPI active configuration mode, the FPGA is configured using a bitstream stored in the SPI flash device. During configuration, the maximum clock frequency for the flash device is specified in SPI Active. When the FPGA is in user mode, you can access the flash at the flash device's maximum clock frequency (although different SPI flash commands may have different maximum clock frequencies).

When a configuration bitstream is stored in the SPI flash and the SPI active hardware connection is properly established, the SPI active configuration can automatically start after the power-up. In QFP100F3 packages you are only required to connect the SS_N pin to the SPI_CS_N pin for the SPI active configuration to start automatically. This is additional to other required configuration pin settings depending on the configuration mode you select.

You can also use the SPI flash to store user data during user mode. To read or write the SPI flash during user mode, you must create the SPI flash interface block in the Efinity Interface Designer.

Table 1. SPI Flash Memory Signals (Interface to FPGA Fabric)

SPI Name	Signal	Direction	Description
SCLK	SCLK_OUT	Input	Clock output from FPGA CCK pin to SPI flash memory.
	SCLK_OE	Input	Output enable. Required for multiple controller.
MOSI	MOSI_IN	Output	Required for x2 or x4 data width.
	MOSI_OUT	Input	Data output from FPGA CDI0 to SPI flash memory.
	MOSI_OE	Input	Output enable. Required for x2 data width, x4 data width, or multiple controller.
MISO	MISO_IN	Output	Data input to FPGA CDI1 from SPI flash memory.
	MISO_OUT	Input	Required for x2 or x4 data width.
	MISO_OE	Input	Output enable. Required for x2 or x4 data width.
WP_N	WP_N_IN	Output	Required for x4 data width.
	WP_N_OUT	Input	Data output from FPGA CDI2 pin to SPI flash memory.
	WP_N_OE	Input	Output enable. Required for x4 data width or multiple controller.
HOLD_N	HOLD_N_IN	Output	Required for x4 data width.
	HOLD_N_OUT	Input	Data output from FPGA CDI3 pin to SPI flash memory
	HOLD_N_OE	Input	Output enable. Required for x4 data width or multiple controller.
CS_N	CS_N_OUT	Input	Chip select output from FPGA SS_N pin to SPI flash memory.
	CS_N_OE	Input	Output enable. Required for multiple controller.
CLK	CLK	Input	Required for register interface.

Table 2. SPI Flash Interface Designer Settings

Option	Choices	Notes
Instance Name	User defined
SPI Flash Resource	SPI_FLASH0	Only one resource available.
Enable Register Interface	0, 1	Default: 0 (Disable)
Read/Write Width	×1, ×2, ×4	Default: ×1
Enable Multiple Controller	0, 1	Default: 0 (Disable)
Pin names (various)	User defined	Specify the interface pin names.