When you check your design, the Interface Designer applies design rules to your
configuration settings. The following tables show some of the error and warning
messages you may encounter and explains how to fix them.
clock_rule_capacity (error)
| Message |
Cannot connect to more than <int> different clocks per region (40
rows) on left and right and <int> clocks on the top or bottom |
| To fix |
You are using more clocks than are available. You need to remove some
clocks on the left/right and top/bottom clock regions. |
|
|
| Message |
Connot connect to more than <int> different clocks per region (40
rows) on left and right |
| To fix |
You are using more clocks than are available. You need to remove some
clocks on the left/right clock regions. |
|
|
| Message |
Cannot connect to more than <int> different clocks on top and
bottom |
| To fix |
You are using more clocks than are available. You need to remove some
clocks on the top/bottom clock regions. |
clock_rule_max_count (error)
| Message |
Number of core clock used exceeds max limit of <int> |
| To fix |
Your design has too many clocks (GPIO configured in clkout mode) coming
from the core. You need to remove some clocks |
clock_rule_invalid_name (error)
| Message |
Invalid clock name |
| To fix |
Enter a valid clock name. |
clock_rule_undefined_name (info)
| Message |
Clock <clock name> not defined in the interface, assuming core
generated. |
| To fix |
All clocks in the periphery must be defined in the Interface Designer
(GPIO clock, oscillator, PLL, LVDS GCLK, MIPI D-PHY CLK). This info message
indicates that you have not defined it as an interface block. If the clock
is generated in the core you can ignore this message. |