Design Check: Simple PLL Messages

When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error messages you may encounter and explains how to fix them.

pll_rule_inst_name (error)

Message Instance name is empty
Valid characters are alphanumeric characters with dash and underscore only
To fix Specify a valid instance name.

pll_rule_resource (error)

Message Resource name is empty
Resource is not a valid PLL device instance
To fix Choose a valid PLL resource.

pll_rule_input_freq (error)

Message Input Frequency <float> MHz (after pre-divider) is out of range. Min=<float>MHz Max=<float>MHz
To fix Assign the reference clock frequency to a value within the specified range.

pll_rule_input_freq_limit (error)

Message Input Frequency <float> MHz is out of range. Min=<float>MHz Max=<float>MHz
To fix Assign the right reference clock frequency.

pll_rule_vco_freq (error)

Message VCO frequency is out of range. Freq=<float> Min=<float>MHz Max=<float>MHz
To fix The VCO frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_output_clock (error)

Message At least one output clock must be configured
To fix Configure at least one PLL output clock and specify the output clock pin name.
Message Output clock count is out of range. Min=<int>Max=<int>
To fix You have specified the wrong number of output clocks (too many or none).

pll_rule_pre_divider (error)

Message Pre-divider is out of range. Min=<int> Max=<int>
To fix The pre-divider frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_multiplier (error)

Message Multiplier is out of range. Min=<int> Max=<int>
To fix The multiplier frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_post_divider (error)

Message Post-divider is invalid. Valid values are <list of int>
To fix Choose a post divider value from the list shown.

pll_rule_output_divider (error)

Message Output divider for <clock name> is invalid. Valid values are between 1-256
To fix Choose a value between 1 and 256.

pll_rule_output_number (error)

Message Output number for <clk name> is invalid. It must be between 0 to <int>
To fix The output clocks are numbered (e.g., CLKOUT3). Make sure that the number is within specified range.

pll_rule_clkin_driver (error)

Message ClockIn resource <gpio resource> is not configured as input
To fix Set the GPIO resource that drives the reference input clock to input mode.
Message The GPIO resource <gpio resource> for CLKIN is not configured
To fix Configure the GPIO resource that drives the reference input clock.
Message ClockIn resource <gpio resource> is not configured as pll_clkin connection
To fix Set the GPIO resource that drives the reference input clock to input mode with pll_clkin connection type.

pll_rule_instance_count (error)

Message There can only be one PLL instance
To fix Only create the instance based on the number of available resources in the device.

pll_rule_output_freq (error)

Message Output frequency <float>MHz is out of range. Min=<float>MHz Max=<float>MHz
To fix The output frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_output_name (error)

Message PLL output clock names have to be unique. Duplicates found: <list of string>
To fix You get this error when you use duplicate clock names. Rename them.

pll_rule_invalid_pins (error)

Message Invalid pin names found: <Pin description names>
To fix Update the pin names. Valid characters are alphanumeric characters with dash and underscore only.

pll_rule_oc_cascade (warning)

Message (O * C == 1), PLL cascading is not supported with possible PLL clkout: <clock names>
To fix The listed PLL output clocks cannot be cascaded. Change your design so they are not cascaded.