When you check your design, the Interface Designer applies design rules to your LVDS
settings. The following tables show some of the error and warning messages you may
encounter and explains how to fix them.
lvds_rule_clkout_mode (error)
| Message |
Serial clock name must be configured in clock output mode |
| To fix |
When you are using the clkout mode, you need to specify the serial
clock pin name. |
|
|
| Message |
Parallel clock name must be configured in clock output mode |
| To fix |
When you are using the clkout mode, you need to specify the parallel
clock pin name. |
|
|
| Message |
Parallel clock division <value> is out of range
<min>-<max> |
| To fix |
Parallel clock division factor has to be within specified range (min=1,
max=2). |
|
|
| Message |
Parallel clock division <value> is not an integer |
| To fix |
Parallel clock division factor has to be an integer. |
lvds_rule_output_mode (error)
| Message |
Output name must be configured in data output mode |
| To fix |
Specify a valid pin name. |
|
|
| Message |
Parallel clock name must be configured in data output mode |
| To fix |
When you are using non-bypass mode, you need to specify the parallel
clock pin name. |
|
|
| Message |
Serial clock name must be configured in data output mode |
| To fix |
When you are using non-bypass mode, you need to specify the serial
clock pin name. |
lvds_rule_resource (error)
| Message |
Resource name is empty |
| To fix |
You need to choose a valid resource. |
|
|
| Message |
Resource <string> is not a valid LVDS (Tx/Rx) device
instance |
| To fix |
You need to choose a valid LVDS (Tx/Rx) resource. |
lvds_rule_resource_excluded (error)
| Message |
Resource <resource> is excluded in Package Planner. Please use
another resource |
| To fix |
The pins for the affected resource have been excluded in the Package
Planner, and cannot be assigned. Remove the excluded setting in the Package
Planner or choose another resource. |
lvds_rule_rx_alt_conn (error)
| Message |
Connection type <type> is not supported by the resource |
| To fix |
If you want to use the alternate funciton of an LVDS block, you need to
choose a resource that supports it. You can filter for resources by
alternate function in the Resource Assigner. |
|
|
| Message |
The resource only supports normal connection type |
| To fix |
You need to choose the normal connection type or assign a different
resource that supports the connection type you want to use. You can filter
for resources by alternate function in the Resource Assigner. |
lvds_rule_alt_conn (warning)
| Message |
Connection type <type> must be used by valid PLL |
| To fix |
The LVDS block is connected to a PLL clock input but is the resource
you assigned does not support the pll_clkin alternate function. Choose a
different resource that supports it. You can filter resources by alternate
function in the Resource Assigner. |
|
|
| Message |
Connection type <type> cannot be used on an unbonded
resource |
| To fix |
You get this error if the resource you choose is not available in the
FPGA/package combination you are using. Choose
another resource. |
|
|
| Message |
pll_clkin connection to PLL clock source not being used in
<instance> |
| To fix |
The LVDS block is set to be a PLL reference clock (pll_clkin connection
type) but the PLL is not configured to use it. Make sure that the clock you
are choosing in the PLL is associated with this LVDS RX's
resource. |
|
|
| Message |
pll_clkin connection to PLL clock source but none of the external clock
source in PLL <instance> is selected |
| To fix |
The LVDS block is set to be a PLL reference clock (pll_clkin connection
type) but the PLL is not configured to use it. In the PLL block, choose
external or dynamic as the Clock Source and make sure that the clock you are
choosing is associated with this LVDS RX's resource. |
|
|
| Message |
pll_clkin connection to PLL clock source but PLL Clock source on
<instance> is set to core |
| To fix |
The LVDS block is set to be a PLL reference clock (pll_clkin connection
type) but the PLL is not configured to use it. In the PLL block, choose
external or dynamic as the Clock Source and make sure that the clock you are
choosing is associated with this LVDS RX's resource. |
lvds_rule_rx_clock (error)
| Message |
Serial and parallel clocks cannot be the same clock |
| To fix |
You cannot use the same clock for both the serial (FASTCLK) and
parallel (SLOWCLK) clocks. |
|
|
| Message |
Serial clock name is not a PLL output clock |
| To fix |
Use a PLL output clock as the serial (FASTCLK) clock. |
|
|
| Message |
Parallel clock name is not a PLL output clock |
| To fix |
Use a PLL output as the parallel (SLOWCLK) clock. |
|
|
| Message |
Serial and parallel clocks are not from the same PLL instance |
| To fix |
You need to use the same PLL to generate both clocks. |
|
|
| Message |
One of the clock frequencies is 0 |
| To fix |
Set a valid output clock frequency. |
|
|
| Message |
Serial clock frequency has to be <float> times faster than parallel
clock |
| To fix |
Make sure that the PLL output clock frequencies are set correctly.
serial clock frequency = parallel clock frequency *
(serialization / 2) |
lvds_rule_rx_clock (warning)
| Message |
Serial clock <string> phase shift has to be 90 degrees |
| To fix |
Adjust the phase shift for the serial clock to be 90 degrees. |
lvds_rule_rx_config (error)
| Message |
Input name must be configured |
| To fix |
Specify a valid pin name. |
|
|
| Message |
Serial clock name must be configured |
| To fix |
When you are using the LVDS deserializer (deserialization width greater
than 1), you need to specify the serial clock pin name. |
|
|
| Message |
Parallel clock name must be configured |
| To fix |
When you are using the LVDS deserializer (deserialization width greater
than 1), you need to specify the parallel clock pin name. |
|
|
| Message |
Serialization must be configured |
| To fix |
When you are using the LVDS deserializer, you need to set the
serialization width, |
lvds_rule_rx_distance (error)
| Message |
These Rx LVTTL must be placed at least 2 pairs away from LVDS <name>
in order to avoid noise coupling from LVTTL to LVDS: <violated list> |
| To fix |
When using LVDS pins as GPIO, make sure to leave at least 2 pair of
unassigned LVDS pins between any LVDS and LVDS used as LVDS RX in the same
bank. This separation reduces noise. |
lvds_rule_rx_pll_refclk (error)
| Message |
Serial clock name is not a PLL output clock |
| To fix |
Use a PLL output clock as the serial (FASTCLK) clock. |
|
|
| Message |
Parallel clock name is not a PLL output clock |
| To fix |
Use a PLL output as the parallel (SLOWCLK) clock. |
lvds_rule_rx_pll_refclk (warning)
| Message |
Serial clock is expected to be from the following PLL instance:
<resource> |
| To fix |
Only a specific PLL instance can drive the LVDS RX clocks. Change the
PLL to use that resource. |
|
|
| Message |
PLL driving the serial clock should have its reference clock from an
LVDS in pll_clkin connection type |
| To fix |
The PLL's reference clock needs to be driven by a specific resource.
Create an LVDS RX block and set the Connection Type
to pll_clkin. Then use that block as the PLL
reference clock. |
|
|
| Message |
Parallel clock is expected to be from the following PLL instance:
<resource> |
| To fix |
Only a specific PLL instance can drive the LVDS RX clocks. Change the
PLL to use that resource. |
|
|
| Message |
PLL driving the parallel clock should have its reference clock from an
LVDS in pll_clkin connection type |
| To fix |
The PLL's reference clock needs to be driven by a specific resource.
Create an LVDS RX block and set the Connection Type
to pll_clkin. Then use that block as the PLL
reference clock. |
lvds_rule_tx_clock (error)
| Message |
Serial and parallel clocks cannot be the same clock |
| To fix |
You cannot use the same clock for both the serial (FASTCLK) and
parallel (SLOWCLK) clocks. |
|
|
| Message |
Parallel clock <name> phase shift has to be 0 degree |
| To fix |
Set the Parallel clock <name>'s phase shift to 0 degree |
|
|
| Message |
Serial clock name is not a PLL output clock |
| To fix |
Use a PLL output clock as the serial (FASTCLK) clock. |
|
|
| Message |
Parallel clock name is not a PLL output clock |
| To fix |
Use a PLL output as the parallel (SLOWCLK) clock. |
|
|
| Message |
Serial and parallel clocks are not from the same PLL instance |
| To fix |
You need to use the same PLL to generate both clocks. |
|
|
| Message |
One of the clock frequencies is 0 |
| To fix |
Set a valid output clock frequency. |
|
|
| Message |
Serial clock frequency has to be <float> times faster than parallel
clock |
| To fix |
Make sure that the PLL output clock frequencies are set correctly.
serial clock frequency = parallel clock frequency *
(serialization / 2) |
|
|
| Message |
Serial clock <string> phase shift has to be 45 degrees |
| To fix |
Adjust the phase shift for the serial clock to be 45 degrees. When
serialization width is 3, serial clock phase shift has to be 45
degree. |
|
|
| Message |
Allowed serial clock (<name>) phase shift values: 45, 90, 135
degrees |
| To fix |
Set to the allowed phase shift values when serialization width is not
3. |
lvds_rule_tx_distance (error)
| Message |
These Tx LVTTL must be placed at least 2 pairs away from LVDS <name>
in order to avoid noise coupling from LVTTL to LVDS: <violated
list> |
| To fix |
When using LVDS pins as GPIO, make sure to leave at least 2 pair of
unassigned LVDS pins between any LVDS and LVDS used as LVDS TX in the same
bank. This separation reduces noise. |
lvds_rule_clkout_ser_disabled (error)
| Message |
Output clock name must be configured in clock output mode with
serialization disabled |
| To fix |
Specify the output clock name. |
lvds_rule_rx_pll_feedback (warning)
| Message |
PLL <pll_slow_inst_name> driving the LVDS Rx clock sources should
have its feedback mode set to core for optimized performance |
| To fix |
Set feedback mode of the PLL to core for better performance. |
lvds_rule_rx_parallelclk_to_refclk_freq (error)
| Message |
Parallel clock frequency (<value>MHz) to PLL reference clock
frequency (<value>MHz) ratio is expected to be an integer |
| To fix |
Specify an integer value. |
lvds_rule_alt_config (error)
| Message |
<resource> can only be used as an LVDS PLL reference clock |
| To fix |
If LVDS Rx does not have pout (data) pins, then only can be used as a
reference clock (i.e. GPIOB_RX_CLK). |