Output Clock Swapping

When you perform a design check or generate constraints, the software tries to find a legal routing for the PLL output clock (clkout0, clkout1, or clkout2). To create a legal routing, it may swap the clock output setting (for example, clkout0 to clkout1 or vice versa). When this swap happens, the software updates the PLL block to reflect the change. The original naming is preserved and the result is functionally equivalent.