Using the LVDS Block

The LVDS block defines the functionality of the LVDS pins. You can choose whether the block is a transmitter (TX) or receiver (RX).

LVDS TX

The maximum LVDS rate is 800 Mbps. The serial clock frequency = parallel clock frequency * (serialization / 2).

  • For a serialization of 3, the fast clock must be phase shifted by 45°.
  • For all other serializations, the fast clock must be phase shifted by 90°.

Both clocks must come from the same PLL. The software issues an error if you do not follow these guidelines.

Note: Efinix® recommends that you select values of 2 or higher for the PLL post divider and output divider. These settings provide a more stable clock signal for faster speeds.

The serial clock (also known as the fast clock) outputs data to the pin, the parallel clock (also known as the slow clock) transfers it from the core. An equation defines the relationship between the clocks. For LVDS TX the parallel clock captures data from the core and the serial clock outputs it to the LVDS buffer.

New data is output on both edges of the serial clock.

LVDS RX

The serial clock (also known as the fast clock) captures data from the pin, the parallel clock (also known as the slow clock) transfers it to the core. An equation defines the relationship between the clocks.

The maximum LVDS rate is 800 Mbps. The serial clock frequency = parallel clock frequency * (serialization / 2). The serial clock should use the 90 degree phase shift and both clocks must come from the same PLL. The software issues a warning of you do not use these guidelines.

Note: Efinix® recommends that you select 2 or higher for the PLL post divider and output divider. These settings provide a more stable clock signal for faster speeds. If the LVDS receiver speed is 600 Mbps or higher, the Efinity® software issues a warning if you select 1 as the PLL post divider and output divider values.