Using the DDR Block

You can add one DDR interface block to your design (see which packages support DDR). Configuration settings are arranged in tabs.

• Base—Choose the resource and specify an instance name. This name becomes the prefix for all of the DDR interface signals. Also choose the Memory Type (DDR3, LPDDR2, or LPDDR3).
• Configuration—Specify the type of memory to which you want to connect. You can choose a preset configuration by clicking Select Preset, or you can manually specify the DQ width, speed, and density. T20 and T35 FPGAs support a x16 DQ width; T55, T85, and T120 FPGAs support x16 or X32 DQ widths.
• Advanced Options—Make the following settings:

  Accordion Tab	Settings
  FPGA Settings	Choose the input and output termination. The choices vary depending on the memory type you select in the Base tab.
  Memory Mode Register Settings	Memory-specific settings. The choices vary depending on the memory type you select in the Base tab.
  Memory Timing Settings	Specify the timing settings for the memory device you are using.
  Controller Settings	Select how the memory address is mapped, and auto-power-down and self refresh behavior.
  Gate Delay Tuning Settings	Optionally enable a gate delay override and specify coarse and fine delay tuning.

• Control—Optionally enable PHY calibration or soft reset. If you use this option, Efinix recommends that you keep the default pin names.
• AXI 0—Enable the AXI interface target 0 and specify the name of the AXI input clock pin. Efinix recommends that you keep the default names.
• AXI 1—Enable the AXI interface target 1 and specify the name of the AXI input clock pin. Efinix recommends that you keep the default names.