Design Check: DDR Messages

When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error messages you may encounter and explains how to fix them.

ddr_rule_adv_density (error)

Message	Row width / column width have to be greater than 0 when advanced density setting is enabled
To fix	Adjust the row width / column width for advanced density setting.

ddr_rule_config_settings (error)

Message	Invalid combination of configuration settings
To fix	Select only the available configuration settings under Configuration tab.

ddr_rule_controller_settings (error)

Message	Invalid selection in Controller Settings: <setting>
To fix	Select only the available configuration settings under Advance Setting > Controller tab.

ddr_rule_empty_pins (error)

Message	Empty pin names found
To fix	If you enable AXI target or the calibration, you must enter pin name for pins in that category.

ddr_rule_fpga_settings (error)

Message	Invalid selection in FPGA Settings: <setting>
To fix	Select only the available configuration settings under Advance Setting > FPGA tab.

ddr_rule_gate_delay_settings (error)

Message	Values invalid in Gate Delay Tuning Settings: <setting>
To fix	Select only the available configuration settings under Advance Setting > Gate Delay Tuning tab.

ddr_rule_invalid_pins (error)

Message	Invalid pin names found: <pin names>
To fix	Update the pin names. Valid characters are alphanumeric characters with dash and underscore only.

ddr_rule_lvds_ref_clock (warning)

Message	It is not recommended to use LVDS Rx as reference clock resource to drive the PHY Clock, as the DDR interface will not be initialized during configuration phase. We recommend that users reset the DDR interface after entering user mode to ensure the DDR memory was fully initialized.
To fix	Use another PLL reference clock resource other than LVDS RX to drive the DDR PHY Clock.

ddr_rule_memory_settings (error)

Message	Invalid selection in Memory Mode Register Settings: <setting>
To fix	Select only the available configuration settings under Advance Setting > Memory Mode Register tab.

ddr_rule_memory_settings (warning)

Message	For the <speed grade> speed grade, RL/WL values are below the minimum. (Suggested minimum value: RL=<>, WL=<>)
To fix	Change the Read/Write Latency value (Advanced Options tab > Memory Mode Register Settings subtab) to be equal to or greater than the minimum suggested value.

ddr_rule_mem_timing_settings (error)

Message	Values out of valid range in Memory Timing Settings: <setting>
To fix	Select only the available configuration settings under Advance Setting > Memory Timing tab.

ddr_rule_minimal_usage (error)

Message	None of the AXI targets are enabled
To fix	Configure any of the AXI target when the DDR block is instantiated.

ddr_rule_phy_clock (error)

Message	Output clock 0 in PLL resource <pll> for PHY Clock not configured
To fix	Configure the PLL instance that drives the PHY Clock Input, with only enabling the output clock 0.

Message	Output clock 0 in PLL <pll> not configured
To fix	Configure the output clock 0 of the PLL instance that drives the PHY Clock Input.

ddr_rule_phy_clock (warning)

Message	This configuration is not recommended as it can result in lower DDR performance and we recommend that users reset the DDR interface after entering user mode to ensure the DDR memory was fully initialized
To fix	Update the PLL Instance to use internal or local feedback mode for better DDR performance.

ddr_rule_phy_clock_freq (error)

Message	DDR PHY Clock frequency <freq>MHz exceeds maximum range <freq>MHz
To fix	The output clock frequency divided by possible clk divider value must be less or equal to 100 MHz.

ddr_rule_pll_feedback (error)

Message	Feedback mode for PLL <instance> can only be set to internal or local when DDR is configured
To fix	Change the feedback mode for the PLL instance.

ddr_rule_ref_clock_freq (warning)

Message	DDR may require auto-calibration for performance above 800 Mbps (Ref Clock Freq: {}MHz)
To fix	DDR may require auto-calibration for performance above 800 Mbps. See the DDR Hard Memory Controller-Calibration User Guide for more information.

ddr_rule_resource (error)

Message	Resource name is empty
To fix	Enter a valid resource name.

Message	Resource <name> is not a valid DDR device instance
To fix	The resource you specified does not exist. Check whether you have a typo in the resource name.

ddr_rule_resource_excluded (error)

Message	Resource <resource> is excluded in Package Planner. Please use another resource
To fix	The pins for the affected resource have been excluded in the Package Planner, and cannot be assigned. Remove the excluded setting in the Package Planner or choose another resource.