About the Simple PLL Interface

T4 and T8 FPGAs in F49 and F81 packages have 1 PLL to synthesize clock frequencies. The PLL's reference clock input comes from a dedicated GPIO's alternate input pin. The PLL consists of a pre-divider counter (N counter), a feedback multiplier counter (M counter), post-divider counter (O counter), and an output divider per clock output.

Figure 1. Trion PLL Block Diagram
The counter settings define the PLL output frequency: where:
FPFD = FIN / N
FVCO = FPFD x M
FOUT = FVCO / (O x Output divider)
FVCO is the voltage control oscillator frequency
FOUT is the output clock frequency
FIN is the reference clock frequency
FPFD is the phase frequency detector input frequency
Note: The reference clock must be between 10 and 50 MHz.
The PFD input must be between 10 and 50 MHz.
The VCO frequency must be between 500 and 1,200 MHz.

Unlike other Trion® FPGAs, the Trion PLL output locks on the negative clock edge (not the positive edge). When you are using two or more clock outputs, they are aligned on the falling edge. If the core register receiving the clock is positive edge triggered, Efinix recommends inverting the clock outputs so they are correctly edge aligned.

Figure 2. PLL Output Aligned with Negative Edge
Table 1. PLL Pins
Port Direction Description
CLKIN Input Reference clock. This port is also a GPIO pin; the GPIO pins' alternate function is configured as a reference clock.
RSTN Input Active-low PLL reset signal. When asserted, this signal resets the PLL; when de-asserted, it enables the PLL. Connect this signal in your design to power up or reset the PLL. Assert the RSTN pin for a minimum pulse of 10 ns to reset the PLL.
CLKOUT0
CLKOUT1
CLKOUT2
 Output PLL output. The designer can route these signals as input clocks to the core's GCLK network.
LOCKED1 Output Goes high when PLL achieves lock; goes low when a loss of lock is detected. Connect this signal in your design to monitor the lock status. This signal is analog asynchronous.
Table 2. PLL SettingsConfigure these settings in the Efinity® Interface Designer.
Setting Allowed Values Notes
N counter 1 - 15 (integer) Pre-divider
M counter 1 - 255 (integer) Multiplier
O counter 1, 2, 4, 8 Post-divider
Output divider 2, 4, 8, 16, 32, 64, 128, 256 Output divider per output
1 The circuitry that generates the lock signal relies on a reference clock edge to transition the lock signal. A sudden removal of the reference clock will result in there being no positive clock edge with which to change the lock state from 1 back to 0. Therefore, the lock signal will remain on 1.