About the MIPI Interface

The MIPI CSI-2 interface is the most widely used camera interface for mobile.1. You can use this interface to build single- or multi-camera designs for a variety of applications.

Trion FPGAs include two hardened MIPI D-PHY blocks (4 data lanes and 1 clock lane) with MIPI CSI-2 IP blocks. The MIPI RX and MIPI TX can operate independently with dedicated I/O banks.

Trion FPGAs can include hardened MIPI D-PHY blocks (4 data lanes and 1 clock lane) with MIPI CSI-2 IP blocks. The MIPI RX and MIPI TX can operate independently with dedicated I/O banks.

Note: The MIPI D-PHY and CSI-2 controller are hard blocks; users cannot bypass the CSI-2 controller to access the D-PHY directly for non-CSI-2 applications.
The MIPI TX/RX interface supports the MIPI CSI-2 specification v1.3 and the MIPI D-PHY specification v1.1. It has the following features:
  • Programmable data lane configuration supporting 1, 2, or 4 lanes
  • High-speed mode supports up to 1.5 Gbps data rates per lane
  • Operates in continuous and non-continuous clock modes
  • 64 bit pixel interface for cameras
  • Supports Ultra-Low Power State (ULPS)
Table 1. MIPI Supported Data Types
Supported Data Type Format
RAW RAW6, RAW7, RAW8, RAW10, RAW12, RAW14
YUV YUV420 8-bit (legacy), YUV420 8-bit, YUV420 10-bit, YUV420 8-bit (CSPS), YUV420 10-bit (CSPS), YUV422 8-bit, YUV422 10-bit
RGB RGB444, RGB555, RGB565, RGB666, RGB888
User Defined 8 bit format

With more than one MIPI TX and RX blocks, Trion® FPGAs support a variety of video applications.

Figure 1. MIPI Example System
1 Source: MIPI Alliance https://www.mipi.org/specifications/csi-2