Design Check: Advanced PLL Messages

When you check your design, the Interface Designer applies design rules to your configuration settings. The following tables show some of the error messages you may encounter and explains how to fix them.

pll_rule_inst_name (error)

Message Instance name is empty
Valid characters are alphanumeric characters with dash and underscore only
To fix Specify a valid instance name.

pll_rule_input_freq (error)

Message Input Frequency <float> MHz (after pre-divider) is out of range. Min=<float>MHz Max=<float>MHz
To fix Assign the reference clock frequency to a value within the specified range.

pll_rule_input_freq_limit (error)

Message Input Frequency <float> MHz is out of range. Min=<float>MHz Max=<float>MHz
To fix Assign the right reference clock frequency.

pll_rule_multiplier (error)

Message Multiplier is out of range. Min=<int> Max=<int>
To fix The multiplier frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_pre_divider (error)

Message Pre-divider is out of range. Min=<int> Max=<int>
To fix The pre-divider frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_post_divider (error)

Message Post-divider is invalid. Valid values are <list of int>
To fix Choose a post divider value from the list shown.

pll_rule_output_clock (error)

Message At least one output clock must be configured
To fix Configure at least one PLL output clock and specify the output clock pin name.
Message Output clock count is out of range. Min=<int>Max=<int>
To fix You have specified the wrong number of output clocks (too many or none).

pll_rule_output_number (error)

Message Output number for <clk name> is invalid. It must be between 0 to <int>
To fix Make sure that the number is within specified range.

pll_rule_resource (error)

Message Resource name is empty
Resource is not a valid PLL device instance
To fix Choose a valid PLL resource.

pll_rule_output_name (error)

Message PLL output clock names have to be unique. Duplicates found: <list of string>
To fix You get this error when you use duplicate clock names. Rename them.

pll_rule_output_divider (error)

Message Output divider for <clock name> is invalid.
To fix Choose a value from the specified list.

pll_rule_refclk (error)

Message Bonded external reference clock pin has to be specified in dynamic mode
To fix When using dynamic as the Clock Source, the PLL expects to find the resource for the external clock(s). Add a GPIO or LVDS RX block in input mode, set the Connection Type to pll_clkin, and assign it to the resource shown in the PLL Properties tab under Dynamic Clock.
Message External refclk pin has to be set in external mode
To fix When using external as the Clock Source, the PLL expects to find the resource for the external clock. Add a GPIO or LVDS RX block in input mode, set the Connection Type to pll_clkin, and assign it to the resource shown in the PLL Properties tab under External Clock.
Message Reference clock at <resource> connected to external clock pin {0|1} has not been defined
To fix The PLL expects to find the resource for the external clock. Add a GPIO or LVDS RX block in input mode, set the Connection Type to pll_clkin, and assign it to the resource shown in the PLL Properties tab under External Clock.
Message Invalid external clock {0|1} resource selected: Resource Unbonded
To fix In the FPGA/package combination you are using, you cannot use the external clock resoure specified because it is not available in the package.
Message ClockIn resource {} is not configured as pll_clkin connection
To fix The clock set as reference clock for PLL should have its connection type set to pll_clkin.
Message The resource for CLKIN[<index>] is not configured
To fix The PLL expects to find the resource for the PLL clockin. Add a GPIO block in input mode, set the Connection Type to pll_clkin, and assign it to the correct resource.
Message Core refclk pin has to be specified in core mode
To fix When using core as the Clock Source, you need to specify the pin name.
Message Both core refclk pins have to be specified in dynamic mode
To fix When using dynamic as the Clock Source, you need to specify the names for the core clocks 0 and 1.

pll_rule_feedback_clock (error)

Message Feedback clock name is required with non-internal feedback
To fix You need to specify a clock pin name when you are not using internal feedback mode.
Message Feedback clock name <string> is not from the same PLL
To fix You need to use one of the output clocks from the PLL you are configuring as the feedback clock. You cannot use an output clock from a different PLL.
Message Feedback clock in local mode has to connect to output clock 0
To fix When Feedback Mode is Local, you can only use output clock 0 for feedback.
Message Total non-internal feedback division factor <int> is out of range. Max=255
To fix The division factor (multiplier * post divider * output divider) must be within the specified range.
Message Non-internal feedback multiplier <int> is out of range. Max=128
To fix The multiplier setting must be within the specified range when in non-internal feedback mode.
Message Feedback clock <string> is not connected to pll clkout
To fix The feedback clock you are using needs to be one of the output clocks from the PLL.

pll_rule_feedback_clock (info)

Message Feedback clock phase shift is not 0-degree, check that the feedback clock is in-phase with the reference clock.
To fix Set the feedback clock phase to 0 degrees in the PLL Clock Calculator. Efinix recommends a 0 degree phase for feedback clocks.

pll_rule_phase_shift (error)

Message Output divider of clock <string> has to be 2 when phase shift is any of this values: 180,270
To fix Set output clock divider to 2 when phase shift is 180 or 270.
Message Output divider of clock <string> has to be 4 when phase shift is 45 or 135
To fix Set output clk divider to 4 when phase shift is 45 or 135.
Message Output divider of clock <string> has to be 2, 4, or 6 when phase shift is 90
To fix Set output clk divider to 2, 4, or 6 when phase shift is 90.

pll_rule_vco_freq (error)

Message VCO frequency is out of range. Freq=<float> Min=<float>MHz Max=<float>MHz
To fix The VCO frequency needs to be within the range specified. Adjust the parameters to meet that requirement.

pll_rule_output_freq (error)

Message Output frequency <float>MHz is out of range. Min=<float>MHz Max=<float>MHz
To fix The output frequency needs to be within the range specified. Adjust the parameters to meet that requirement.
Message Output frequency <float>MHz driving DDR is out of range. Min=<float>MHz Max=<float>MHz
To fix The clock driving the DDR input clock needs to be within the range specified. Adjust the parameters to meet that requirement. This is for a clock driving the DDR input clock with the limit depends on the DDR speedgrade configured by user.

pll_rule_phase_shift_post_divider (warning)

Message Post-divider should be greater than 1 when there is an output clock with non-zero phase shift
To fix Set the post-divider to more than 1.

pll_rule_pll_freq (error)

Message PLL Frequency is out of range, Freq=<value> Min=<min>MHz Max=<max>MHz
To fix The maximum post-divided VCO clock fmax is out of range. Change the PLL clock calculator settings so that it is in range.

pll_rule_non_internal_vco_lower_bound (warning)

Message VCO frequency should be greater than 1.6GHz in local/core feedback mode
To fix Set the parameters in the instance configuration result in a VCO Frequency to greater than 1.6GHz when feedback mode is set to local or core.

pll_rule_post_div_multi_out_clk (error)

Message Post-divider should be greater than 1 when there are multiple output clocks.
To fix Set the post-divider to more than 1.

pll_rule_clksel_pin (error)

Message Valid characters are alphanumeric characters with dash and underscore only.
To fix Update the pin name for the clock selector pin when reference clock mode is dynamic

pll_rule_fb_freq (error)

Message Feedback frequency <#>MHz is out of range. Min=<>MHz Max=<>MHz
To fix The feedback frequency needs to be within the range specified. Adjust the parameters to meet that requirement.