Configuring the PLL Manually

If you do not want to use the PLL clock calculator, you can manually configure the PLL using the Manual Configuration tab.

Specify the reset and locked pin names. If you do not want to use them, leave the boxes empty.

Choose the feedback mode. The PLL supports these modes:

  • core—The PLL feedback comes from the FPGA core. The feedback clock must be one of the three PLL output clocks. The output clock and reference clock phases are aligned, and the is no core clock delay.Turn on the Use as feedback option for the clock you want to use for feedback.
  • internal—The PLL feedback is internal to the PLL. The reference clock(s) and output clock(s) have no phase relationship.
  • local—The PLL uses clock 0. The feedback is local to the PLL and the output clock is aligned with the reference clock.
Note: In local and core feedback modes, the post-divider and output divider of the clock used for feedback affect the VCO frequency.

Specify the reference clock frequency, multiplier, and pre-divider. The software calculates and displays the resulting VCO frequency. If the VCO is outside of the allowed range, it displays in red.

Choose the post divider. The software calculates and displays the PLL frequency.

The advanced PLL has three output clocks. Enable the output clocks you want to use, and specify the pin name, phase shift, and output divider and whether to use the clock as feedback (core mode only). The software calculates and displays the resulting output frequency.