About the DDR DRAM Interface

The Trion DDR PHY interface supports DDR3, DDR3L, LPDDR3, LPDDR2 memories with x16 or x32 DQ widths (depending on the FPGA) and a memory controller hard IP block. The DDR PHY supports data rates up to 1066 Mbps per lane. The memory controller provides two AXI buses to communicate with the FPGA core.

Note: The DDR PHY and controller are hard blocks; you cannot bypass the DDR DRAM memory controller to access the PHY directly for non-DDR memory controller applications.
Table 1. DDR DRAM Performance
DDR DRAM Interface Voltage (V) Maximum Data Rate (Mbps) per Lane
DDR3 1.5 1066
DDR3L 1.35 1066
LPDDR3 1.2 1066
LPDDR2 1.2 1066

Figure 1. (T20, T35) DDR DRAM Block Diagram

Figure 2. (T55, T85, T120) DDR DRAM Block Diagram

The DDR DRAM block supports an I2C calibration bus that can read/write the DDR configuration registers. You can use this bus to fine tune the DDR PHY for high performance.

Figure 3. DDR DRAM Interface Block Diagram

Table 2. PHY Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Description
CLKIN Input N/A High-speed clock to drive the DDR PHY. A PLL must generate this clock. The clock runs at half of the PHY data rate (for example, 800 Mbps requires a 400 MHz clock).
The DDR DRAM block uses the PLL_BR0 CLKOUT0 resource as the PHY clock.

The PLL reference clock must be driven by I/O pads. The Efinity® software issues a warning if you do not connect the reference clock to an I/O pad. (Using the clock tree may induce additional jitter and degrade the DDR performance.) Refer to About the Advanced PLL Interface for more information about the PLL block.

Important: Efinix strongly recommends that you do not use any LVDS pins (either single-ended I/O or differential pair) as the primary clock to drive the PLL_BR0 or the DDR interface will not be initialized during the configuration phase. Make sure to incorporate a user reset and instantiate the DDR Hard Memory Controller-Reset IP to initialize the DDR interface in user mode. Contact Efinix support if you need LVDS pins as the primary clock for the PLL_BR0 DDR interface
Table 3. AXI Global Signals (Interface to FPGA Fabric)
Signal Direction Clock Domain Description
ACLK_0, ACLK_1 Input N/A AXI clock inputs.
Table 4. AXI Shared Read/Write Signals (Interface to FPGA Fabric)
Signal
x is 0 or 1
 Direction Clock Domain Description
AADDR_x[31:0] Input ACLK_x Address. ATYPE defines whether it is a read or write address. It gives the address of the first transfer in a burst transaction.
ABURST_x[1:0] Input ACLK_x Burst type. The burst type and the size determine how the address for each transfer within the burst is calculated.
AID_x[7:0] Input ACLK_x Address ID. This signal identifies the group of address signals. Depends on ATYPE, the ID can be for a read or write address group.
ALEN_x[7:0] Input ACLK_x Burst length. This signal indicates the number of transfers in a burst.
ALOCK_x[1:0] Input ACLK_x Lock type. This signal provides additional information about the atomic characteristics of the transfer.
AREADY_x Output ACLK_x Address ready. This signal indicates that the slave is ready to accept an address and associated control signals.
ASIZE_x[2:0] Input ACLK_x Burst size. This signal indicates the size of each transfer in the burst.
ATYPE_x Input ACLK_x This signal distinguishes whether is it is a read or write operation. 0 = read and 1 = write.
AVALID_x Input ACLK_x Address valid. This signal indicates that the channel is signaling valid address and control information.
Table 5. AXI Write Response Channel Signals (Interface to FPGA Fabric)
Signal
x is 0 or 1
 Direction Clock Domain Description
BID_x[7:0] Output ACLK_x Response ID tag. This signal is the ID tag of the write response.
BREADY_x Input ACLK_x Response ready. This signal indicates that the master can accept a write response.
BVALID_x Output ACLK_x Write response valid. This signal indicates that the channel is signaling a valid write response.
Table 6. AXI Read Data Channel Signals (Interface to FPGA Fabric)
Signal
x is 0 or 1
 Direction Clock Domain Description
RDATA_x[127:0] Output ACLK_x (T20, T35): Read data.
RDATA_0[255:0] Output ACLK_0 (T55, T85, T120): AXI target 0 read data.
RDATA_1[127:0] Output ACLK_1 (T55, T85, T120): AXI target 1 read data.
RID_x[7:0] Output ACLK_x Read ID tag. This signal is the identification tag for the read data group of signals generated by the slave.
RLAST_x Output ACLK_x Read last. This signal indicates the last transfer in a read burst.
RREADY_x Input ACLK_x Read ready. This signal indicates that the master can accept the read data and response information.
RRESP_x[1:0] Output ACLK_x Read response. This signal indicates the status of the read transfer.
RVALID_x Output ACLK_x Read valid. This signal indicates that the channel is signaling the required read data.
Table 7. AXI Write Data Channel Signals (Interface to FPGA Fabric)
Signal
x is 0 or 1
 Direction Clock Domain Description
WDATA_x[127:0] Input ACLK_x (T20, T35): Write data.
WDATA_0[255:0] Input ACLK_0 (T55, T85, T120): AXI target 0 write data.
WDATA_1[127:0] Input ACLK_1 (T55, T85, T120): AXI target 1 write data.
WID_x[7:0] Input ACLK_x Write ID tag. This signal is the ID tag of the write data transfer.
WLAST_x Input ACLK_x Write last. This signal indicates the last transfer in a write burst.
WREADY_x Output ACLK_x Write ready. This signal indicates that the slave can accept the write data.
WSTRB_x[15:0] Input ACLK_x (T20, T35): Write strobes. This signal indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
WSTRB_0[31:0]
WSTRB_1[15:0]
 Input ACLK_x (T55, T85, T120): Write strobes. This signal indicates which byte lanes hold valid data. There is one write strobe bit for each eight bits of the write data bus.
WVALID_x Input ACLK_x Write valid. This signal indicates that valid write data and strobes are available.
Table 8. DDR DRAM I2C Interface Signals
Signal Direction Description
CFG_SCL_IN Input Clock input.
CFG_SDA_IN Input Data input.
CFG_SDA_OEN Output SDA output enable.
Table 9. DDR DRAM Startup Sequencer Signals
Signal Direction Description
CFG_SEQ_RST Input Active-high DDR configuration controller reset.
CFG_SEQ_START Input Start the DDR configuration controller.
Table 10. DDR DRAM Reset Signal
Signal Direction Description
CFG_RST_N Input Active-low master DDR DRAM reset. After you de-assert RST_N, you need to reconfigure and initialize before performing memory operations.
Table 11. DDR DRAM Pads
Signal Direction Description
DDR_A[15:0] Output Address signals to the memories.
DDR_BA[2:0] Output Bank signals to/from the memories.
DDR_CAS_N Output Active-low column address strobe signal to the memories.
DDR_CKE Output Active-high clock enable signals to the memories.
DDR_CK Output Active-high clock signals to/from the memories. The clock to the memories and to the memory controller must be the same clock frequency and phase.
DDR_CK_N Output Active-low clock signals to/from the memories.The clock to the memories and to the memory controller must be the same clock frequency and phase.
DDR_CS_N Output Active-low chip select signals to the memories.
DDR_DQ[n:0] Bidirectional Data bus to/from the memories. For writes, the pad drives these signals. For reads, the memory drives these signals. These signals are connected to the DQ inputs on the memories. n is 7, 15, or 31 depending on the FPGA and DQ width.
DDR_DM[n] Output Active-high data-mask signals to the memories. n is 1, 1:0, or 3:0 depending on the FPGA and DQ width.
DDR_DQS_N[n:0] Bidirectional Differential data strobes to/from the memories. For writes, the pad drives these signals. For reads, the memory drives these signals. These signals are connected to the DQS inputs on the memories. n is 1, 1:0, or 3:0 depending on the FPGA and DQ width.
DDR_DQS[n:0] Bidirectional
DDR_ODT Output ODT signal to the memories.
DDR_RAS_N Output Active-low row address strobe signal to the memories.
DDR_RST_N Output Active-low reset signals to the memories.
DDR_WE_N Output Active-low write enable strobe signal to the memories.
DDR_VREF Bidirectional Reference voltage.
DDR_ZQ Bidirectional ZQ calibration pin.