About the General-Purpose I/O Logic and Buffer
The GPIO support the 3.3 V LVTTL and 1.8 V, 2.5 V, and 3.3 V LVCMOS I/O standards. The GPIOs are grouped into banks. Each bank has its own VCCIO that sets the bank voltage for the I/O standard.
Each GPIO consists of I/O logic and an I/O buffer. I/O logic connects the core logic to the I/O buffers. I/O buffers are located at the periphery of the device.
The I/O logic comprises three register types:
- Input—Capture interface signals from the I/O before being transferred to the core logic
- Output—Register signals from the core logic before being transferred to the I/O buffers
- Output enable—Enable and disable the I/O buffers when I/O used as output
| GPIO Mode | Description |
|---|---|
| Input |
Only the input path is enabled; optionally registered. If
registered, the input path uses the input clock to control the
registers (positively or negatively triggered).
Select the alternate input path to drive the alternate function of
the GPIO. The alternate path cannot be registered.
Some FPGA/package combinations support DDIO. In DDIO mode, two registers sample the data
on the positive and negative edges of the input clock, creating two
data streams.
|
| Output |
Only the output path is enabled; optionally registered. If
registered, the output path uses the output clock to control the
registers (positively or negatively triggered).
The output register can be inverted.
Some FPGA/package combinations support DDIO. In DDIO mode, two registers sample the data
on the positive and negative edges of the input clock, creating two
data streams.
|
| Bidirectional |
The input, output, and OE paths are enabled; optionally registered.
If registered, the input clock controls the input register, the
output clock controls the output and OE registers. All registers can
be positively or negatively triggered. Additionally, the input and
output paths can be registered independently.
The output register can be inverted.
|
| Clock output | Clock output path is enabled. |
During configuration, all GPIO pins excluding LVDS as GPIO are configured in weak pull-up mode. The LVDS as GPIO pins are tri-stated without a pull-up or pull-down resistor.
By default, unused GPIO pins are tristated and configured in weak pull-up mode. You can change the default mode to weak pull-down in the Interface Designer.
| Package | Supported Features | |
|---|---|---|
| GPIO | LVDS GPIO | |
| T4/T8 | ||
| BGA49 BGA81 |
Schmitt Trigger
Variable Drive Strength
Pull-up
Pull-down
Slew Rate
|
– |
| T8/T13/T20 | ||
| WLCSP80 QFP100F3 QFP144 BGA169 BGA256
|
DDIO
Schmitt Trigger
Variable Drive Strength
Pull-up
Pull-down
Slew Rate
|
Pull-up
|
| T20/T35/T55/T85/T120 | ||
| BGA324 BGA400 BGA484 BGA576 |
DDIO
Schmitt Trigger
Variable Drive Strength
Pull-up
Pull-down
Slew Rate
|
Variable Drive Strength
Pull-up
Slew Rate
|