Enable Internal Reconfiguration

Efinix® FPGAs (except the T4 and T8) have an internal reconfiguration feature that allows you to control reconfiguration of the FPGA from within the FPGA design. Leave this feature disabled unless you want to use internal reconfiguration.

To enable internal reconfiguration:
  1. Click Device Setting > Configuration.
  2. In the Block Editor, turn on Enable Internal Reconfiguration Interface.
  3. Indicate the name of the clock pin that will control the internal reconfiguration.
  4. Define the FPGA pins that the interface uses.
  5. Save.
Note: Refer to AN 010: Using the Internal Reconfiguration Feature to Update Efinix FPGAs Remotely for instructions on how to use this feature.
Table 1. Remote Update Tab Settings
Parameter Choices Notes
Enable Internal Reconfiguration Interface On, off Default: off.
Clock Pin Name User defined Specify the clock pin name used to latch cfg_CBSEL when cfg_ENA is high.
Invert Clock On, off Default: off. Turn on to invert the clock pin.
Image Selector [1:0] Bus Name User defined Multi-image select signals to the internal reconfiguration interface (not package pins). Use these signals to choose which image to load from flash memory. Efinix recommends using the default name.
Image Selector Capture Pin Name User defined When cfg_ENA is high, read the value of cfg_CBSEL. Efinix recommends using the default name.
Configuration Control Pin Name User defined Asynchronous control that initiates reconfiguration. Efinix recommends using the default name.
Error Status Pin Name User defined Status signal. Signal is set to 0 during power-up. Efinix recommends using the default name.
Note: Do not mix 3-byte and 4-byte address modes. All images should use the same setting.