Understanding the RX and TX Pixel Clock
In a MIPI system, the pixel clock is the clock used to transfer the video data to or from the MIPI controller. This document calls it the system pixel clock. The system pixel clock is related to the video resolution. If you are using a standard monitor, you can simply look up the clock specification in the SMPTE/CEA or VESA standards. Alternatively, you can calculate the clock you need.
Generally speaking, you calculate the system pixel clock frequency using the following equation:
Pixel Clock Frequency = Total Horizontal Samples x Total Vertical Lines x Refresh Rate1
where the Total Horizontal Samples and Total Vertical Lines include the blanking period.
In the Interface Designer, the MIPI TX and RX interfaces also have RX and TX pixel clocks. These clocks are not the same as the system pixel clock, however, they are related. These pixel clocks take into account both the system pixel clock and the video data type.
The RX and TX pixel clocks must be equal to or faster than the system pixel clock divided by the number of pixels processed by the MIPI interface each clock cycle. The number of pixels processed per clock depends on the video data type.
For example, if the system pixel clock is running at 150 MHz and using the RGB444 RX data type, which processes 4 pixels per clock, the RX pixel clock must be at least 37.5 MHz.
Video Data Type
The video data type includes the color mode (RAW, RGB, and YUV) and the data format, which together determine the amount of video transmitted every pixel clock (that is, the bandwidth). The overal system bandwidth is simply the system pixel clock times the number of bits of video data transferred each clock cycle.