Using the MIPI Block

You use the MIPI TX and RX blocks to configure the hard MIPI interface. You can add up to two MIPI TX and up to two MIPI RX blocks.

Note: The Efinity® software v2019.1 and later supports the MIPI interface block.

MIPI TX

The MIPI TX Block Editor organizes the settings into tabs. Most settings are simply naming the MIPI signals for your design and specifying timing parameters.

Table 1. Base Tab SettingsThe Base tab is where you set the instance name, choose a resource, and make clock settings.
Setting Choices Notes
Instance Name User defined Specify an instance name.
MIPI TX Resource MIPI_TX0 or MIPI_TX1 Choose which resource to instantiate.
PHY Bandwidth (Mbps) 80 to 1500 Mbps Choose the speed at which to run the D-PHY.
Reference Clock Frequency (MHz) 6.00, 12.00. 19.00, 25.00, 26.00, 27.00, 38.00, 52.00 The software automatically assigns a GPIO resource for the reference clock. You must add a GPIO block in clock output mode and assign it this resource.
Both MIPI resources share the same reference clock. Therefore, you must use the same frequency setting for both instances.
Enable Continuous PHY Clocking On or Off
  • Control Tab—Specify names for control signals. The DPHY and CSI-2 resets are optional. Leave DPHY Reset Pin Name and CSI-2 Reset Pin Name blank if you do not want to use the resets. You must use both resets or neither.
  • Video Tab—Specify names for video signals.
  • Video - ULPS Mode Tab—The MIPI TX block supports the Ultra-Low Power State (ULPS) for the data and clock lanes. In this mode, the lane goes to sleep and does not transmit data. The MIPI block consumes almost no power in ULPS mode. If you want to use ULPS mode, specify the names of the ULPS enter and exit signals for the clock and data lanes.
    Note: The MIPI CSI-2 controller automatically uses escape mode and low-power data transmission for low-power operation. You do not need to enable these modes.
  • Lane Mapping Tab—The MIPI TX block supports 4 data lanes and 1 clock lane. In this tab you choose which lane to associate with the MIPI pad. Select a name from the drop-down list. The lane mapping must be unique, which the software enforces.
  • Timing Tab—In this tab you specify the timing parameters for the clock and data timers.

MIPI RX

The MIPI TX Block Editor organizes the settings into tabs. Most settings are simply naming the MIPI signals for your design and specifying timing parameters.
  • Base Tab—Specify an instance name and choose a MIPI RX resource. Choose MIPI_RX0 or MIPI_RX1.
  • Control Tab—Specify names for control signals.
  • Video Tab—Specify names for video signals.
  • Status Tab—You can choose to enable status signals. Turn on Enable Status and specify the signal names.
  • Lane Mapping Tab—The MIPI TR block supports 4 data lanes and 1 clock lane. In this tab you choose which lane to associate with the MIPI pad. Select a name from the drop-down list. The lane mapping must be unique, which the software enforces.
  • Timing Tab—In this tab you specify the timing parameters for the clock and data timers, as well as the calibration clock frequency.