Efinix, Inc.
  • Get Oriented
    • Interface Blocks
    • Package/Interface Support Matrix
    • Interface Block Connectivity
    • Clocking Interface Blocks
      • Design Check: Clock Messages
    • Designing an Interface
    • Create or Delete a Block
    • Using the Resource Assigner
      • Resource View
      • Importing and Exporting Assignments
        • Interface Scripting File
        • .csv File for GPIO Blocks
    • Editing and Viewing the Package Pinout
      • Selecting a Pin
      • Browsing for Pins
      • Drag-and-Drop Assignments
      • Excluding Pins and Banks
    • Interface Designer Output Files
    • Scripting an Interface Design
  • Device Settings
    • Configuration Interface
      • Enable Internal Reconfiguration
    • Design Check: Configuration Messages
    • I/O Banks Interface
    • I/O Banks
      • Trion I/O Banks
    • Design Check: I/O Bank Messages
  • DDR Interface
    • About the DDR DRAM Interface
    • DDR Interface Designer Settings
    • Using the DDR Block
    • Design Check: DDR Messages
  • GPIO Interface
    • About the General-Purpose I/O Logic and Buffer
      • Simple I/O Buffer
      • Complex I/O Buffer
      • Double-Data I/O
    • Using the GPIO Block
    • Using LVDS as GPIO
    • Using the GPIO Bus Block
    • Design Check: GPIO Messages
  • JTAG User TAP Interface
    • JTAG Mode
    • Using the JTAG User TAP Block
    • Design Check: JTAG User Tap Messages
  • LVDS Interface
    • About the LVDS Interface
      • LVDS TX
      • LVDS RX
    • Using the LVDS Block
    • Create an LVDS TX or RX Interface
      • Create an LVDS TX Interface
      • Create an LVDS RX Interface
    • Design Check: LVDS Messages
  • MIPI CSI-2 Interface
    • About the MIPI Interface
      • MIPI TX
        • MIPI TX Video Data TYPE[5:0] Settings
        • MIPI TX Video Data DATA[63:0] Formats
      • MIPI RX
        • MIPI RX Video Data TYPE[5:0] Settings
        • MIPI RX Video Data DATA[63:0] Formats
      • D-PHY Timing Parameters
      • Understanding the RX and TX Pixel Clock
      • Power Up Sequence
    • Using the MIPI Block
    • Design Check: MIPI Messages
  • PLL Interface
    • About the Simple PLL Interface
    • Using the PLL Block
      • Using the PLL Clock Calculator
      • Set up the PLL Manually
    • Design Check: Simple PLL Messages
  • Advanced PLL Interface
    • About the Advanced PLL Interface
    • Using the PLL Block
      • Using the PLL Clock Calculator
      • Understanding PLL Phase Shifting
      • Configuring the PLL Manually
      • Output Clock Swapping
    • Design Check: Advanced PLL Messages
  • Oscillator Interface
    • Oscillator
    • Using the Oscillator Block
    • Design Check: Oscillator Messages
  • SPI Flash Interface
    • About the SPI Flash Memory
    • Using the SPI Flash Interface
    • Design Check: SPI Flash Messages
  • Interface Floorplans

PLL Interface

The following sections describe the simple PLL and how to use it. Refer to Interface Blocks to find out if your FPGA supports the simple PLL.

Note: At startup, Efinix recommends that you hold the PLL in reset until the PLL's reference clock source is stable.
  • About the Simple PLL Interface
  • Using the PLL Block
  • Design Check: Simple PLL Messages

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