Simple I/O Buffer

T4/T8 FPGAs in F49 and F81 packages have simple I/O interface with logic and a buffer.

Figure 1. T8/T4 I/O Interface Block

Table 1. GPIO Signals
Signal Direction Description
I Output Input data from the GPIO pad to the core fabric.
ALT Output Alternative input connection (in the Interface Designer, the input Register Option is none). Alternative connections are GCLK, GCTRL, and PLL_CLKIN.
O Input Output data to GPIO pad from the core fabric.
OE Input Output enable from core fabric to the I/O block. Can be registered.
OUTCLK Input Core clock that controls the output and OE register. This clock is not visible in the user netlist.
INCLK Input Core clock that controls the input register. This clock is not visible in the user netlist.
Table 2. GPIO Pads
Signal Direction Description
IO Bidirectional GPIO pad.