D-PHY Timing Parameters

During CSI-2 data transmission, the MIPI D-PHY alternates between low power mode and high-speed mode. The D-PHY specification defines timing parameters to facilitate the correct hand-shaking between the MIPI TX and MIPI RX during mode transitions.

You set the timing parameters to correspond to the specifications of your hardware in the Efinity® Interface Designer.
  • RX parameters—TCLK-SETTLE, THS-SETTLE (see Table 1)
  • TX parameters—TCLK-POST, TCLK-TRAIL, TCLK-PREPARE, TCLK-ZERO, TCLK-PRE, THS-PREPARE, THS-ZERO, THS-TRAIL (see Table 4)
Figure 1. High-Speed Data Transmission in Bursts Waveform
Figure 2. Switching the Clock Lane between Clock Transmission and Low Power Mode Waveform

Table 1. D-PHY Timing Specifications
Parameter Description Min Typ Max Unit
TCLK-POST Time that the transmitter continues to send HS clock after the last associated Data Lane has transitioned to LP Mode. Interval is defined as the period from the end of THS-TRAIL to the beginning of TCLK-TRAIL. 60 ns + 52*UI – – ns
TCLK-PRE Time that the HS clock shall be driven by the transmitter prior to any associated Data Lane beginning the transition from LP to HS mode. 8 – – UI
TCLK-PREPARE Time that the transmitter drives the Clock Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission. 38 – 95 ns
TCLK-SETTLE Time interval during which the HS receiver should ignore any Clock Lane HS transitions, starting from the beginning of TCLK-PREPARE. 95 – 300 ns
TCLK-TRAIL Time that the transmitter drives the HS-0 state after the last payload clock bit of a HS transmission burst. 60 – – ns
TCLK-PREPARE + TCLK-ZERO TCLK-PREPARE + time that the transmitter drives the HS-0 state prior to starting the Clock. 300 – – ns
THS-PREPARE Time that the transmitter drives the Data Lane LP-00 Line state immediately before the HS-0 Line state starting the HS transmission 40 ns + 4*UI – 85 ns + 6*UI ns
THS-SETTLE Time interval during which the HS receiver shall ignore any Data Lane HS transitions, starting from the beginning of THS-PREPARE.
The HS receiver shall ignore any Data Lane transitions before the minimum value, and the HS receiver shall respond to any Data Lane transitions after the maximum value.
 85 ns + 6*UI – 145 ns + 10*UI ns
THS-TRAIL Time that the transmitter drives the flipped differential state after last payload data bit of a HS transmission burst. max( n*8*UI, 60 ns + n*4*UI)1 – – ns
TLPX Transmitted length of any Low-Power state period 50 – – ns
THS-PREPARE + THS-ZERO THS-PREPARE + time that the transmitter drives the HS-0 state prior to transmitting the Sync sequence. 145 ns + 10*UI – – ns
1 Where n = 1 in Forward-direction HS mode and n = 4 for Reverse-direction HS mode.