Double-Data I/O

Some Trion FPGAs support double data I/O (DDIO) on certain input and output registers. In this mode, the DDIO register captures data on both positive and negative clock edges. The core receives 2 bit wide data from the interface.

In normal mode, the interface receives or sends data directly to or from the core on the positive and negative clock edges. In resync mode, the interface resynchronizes the data to pass both signals on the positive clock edge only.

Not all GPIO support DDIO; additionally, LVDS as GPIO (that is, single ended I/O) do not support DDIO functionality.

Not all GPIO support DDIO; additionally, LVDS as GPIO (that is, single ended I/O) do not support DDIO functionality.

Note: The Resource Assigner in the Efinity® Interface Designer shows which GPIO support DDIO.
Note: The Resource Assigner in the Efinity® Interface Designer shows which GPIO support DDIO.

Figure 1. DDIO Input Timing Waveform

Figure 2. DDIO Output Timing Waveform